JPH0322435U - - Google Patents
Info
- Publication number
- JPH0322435U JPH0322435U JP16471488U JP16471488U JPH0322435U JP H0322435 U JPH0322435 U JP H0322435U JP 16471488 U JP16471488 U JP 16471488U JP 16471488 U JP16471488 U JP 16471488U JP H0322435 U JPH0322435 U JP H0322435U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- duty ratio
- output
- delay circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
第1図は本考案の一実施例を示すブロツク図で
、第2図はその各部のパルス波形を示すタイムチ
ヤートである。第3図は本考案の他の実施例を示
すブロツク図で、第4図はその各部のパルス波形
を示すタイムチヤートである。第3図は従来の3
分周回路を示すブロツク図で、第4図はその各部
のパルス波形を示すタイムチヤートである。
1……カウンタ、7……Dフリツプ・フロツプ
(遅延回路)、8……オアゲート。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing pulse waveforms of various parts thereof. FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a time chart showing pulse waveforms at various parts thereof. Figure 3 shows the conventional 3
This is a block diagram showing the frequency dividing circuit, and FIG. 4 is a time chart showing the pulse waveforms of each part of the circuit. 1... Counter, 7... D flip-flop (delay circuit), 8... OR gate.
補正 平2.8.6
図面の簡単な説明を次のように補正する。
明細書の第7頁第20行目の「第3図」を「第
5図」と補正する。
明細書の第8頁第1行目の「第4図」を「第6
図」と補正する。Amendment 2.8.6 The brief description of the drawing is amended as follows. "Figure 3" on page 7, line 20 of the specification is corrected to "Figure 5." ``Figure 4'' in the first line of page 8 of the specification has been replaced with ``Figure 6''.
Correct it to "Fig."
Claims (1)
を自然数として2N+1個カウントする毎にクリ
アされるカウンタと、このカウンタから出力され
る周期(2N+1)Tでデユーテイ比N2N+1
のパルスを1/2Tだけ遅延させる遅延回路と、こ
の遅延回路の出力パルスと上記デユーテイ比N2
N+1のパルスを入力するオアゲートとを備え、
そのオアゲート出力を分周出力パルスとして取り
出すようにしてなる2N+1分周回路。 (2) 前記遅延回路が前記入力パルスをクロツク
とするDフリツプ・フロツプまたはDタイプのト
ランスペアレントラツチ回路で構成されている請
求項1記載の2N+1分周回路。[Scope of claims for utility model registration] (1) Input pulses with period T and duty ratio 1/2 are
A counter that is cleared every time 2N+1 is counted as a natural number, and a duty ratio of N2N+1 with the period (2N+1)T output from this counter.
A delay circuit that delays the pulse by 1/2T, an output pulse of this delay circuit, and the above duty ratio N2
Equipped with an OR gate that inputs N+1 pulses,
A 2N+1 frequency divider circuit that extracts the OR gate output as a frequency divided output pulse. (2) The 2N+1 frequency divider circuit according to claim 1, wherein said delay circuit is constituted by a D flip-flop or a D type transparent latch circuit using said input pulse as a clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16471488U JPH0322435U (en) | 1988-12-20 | 1988-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16471488U JPH0322435U (en) | 1988-12-20 | 1988-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322435U true JPH0322435U (en) | 1991-03-07 |
Family
ID=31699623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16471488U Pending JPH0322435U (en) | 1988-12-20 | 1988-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322435U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001319285A (en) * | 2000-05-11 | 2001-11-16 | Ricoh Elemex Corp | Concentrated control system for meter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376617A (en) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | Odd number frequency-dividing circuit |
| JPS63203008A (en) * | 1987-02-18 | 1988-08-22 | Fujitsu Ltd | Circuit for dividing frequency into odd number of parts |
-
1988
- 1988-12-20 JP JP16471488U patent/JPH0322435U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6376617A (en) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | Odd number frequency-dividing circuit |
| JPS63203008A (en) * | 1987-02-18 | 1988-08-22 | Fujitsu Ltd | Circuit for dividing frequency into odd number of parts |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001319285A (en) * | 2000-05-11 | 2001-11-16 | Ricoh Elemex Corp | Concentrated control system for meter |