JPH02246621A - A/d converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to an A/D converter, and more particularly, to an A/D converter having a circuit that self-corrects nonlinearity errors. Recently, 1-chip A with 14-bit and 16-bit resolution has been introduced.
/D converters have been developed, but A/D converters with 12 vias or more have been developed.
If the D converter is an LSI, some kind of correction is required.For example, the offset voltage and reference voltage of the comparator may be adjusted to keep the nonlinearity error of the A/D converter within the desired range. are doing. Correction methods are divided into two types:
One is to correct manufacturing process variations by laser trimming etc. at the time of factory shipment, and the other is to correct manufacturing process variations by laser trimming etc.
This is a method in which a self-correction circuit is built into I. The technical background of the present invention is such a matter. [Prior art] A conventional A/D converter with a built-in self-correction circuit is
For example, the one shown in FIG. 5.6 is known. FIG. 5 is a block diagram of an A/D converter called a successive approximation type, and this type of converter takes a conversion time of several to several hundred μs.
It is most often used as a medium-speed, medium-accuracy conversion method with a resolution of about 12. The A/D converter shown in FIG. 5 is roughly divided into a chopper-type comparator 1, a successive approximation register 2,
It is composed of an offset correction register 3, a D/A conversion circuit 4, and a switch 5.6. The operating principle is initially D/A
The MSB (most significant bit) of the conversion circuit 4 is set to 1'', and then the switch 5.6 is closed to compare the current D/A conversion output (in this case, the analog input voltage Vi is compared with the comparator 1. If , the MSB remains set to 1 in the successive approximation register 2, and if otherwise, the MSB is returned to 0 and then the comparison operation moves to the 2nd bit.The 2nd bit is also set as in the case of MSH. "1"
Set. Now, MSB=1 and the output of the D/A conversion circuit 4 becomes vrs. At this time, if , the second bit is also kept at "1" and the process moves to the third bit. By performing successive approximation operation in this way,
The digital value up to the LSB (least significant bit) is determined. Also, when the power is turned on, the contents of the offset correction register 3 are set according to the output of the comparator 1, and the contents of the D/A conversion circuit 4 are set.
The non-linearity error is self-corrected by adjusting the offset voltage of AVH. A concrete circuit explaining this operation is shown in FIG. In the figure, 10 is a resistor ladder circuit consisting of resistors Rl-Rh, with AVR" (for example, 5V) and AVR" (for example, 5V) at both ends.
A constant voltage of VR-(QV) is applied. Further, the resistance ladder circuit 10 is included in the D/A conversion circuit 4, and is
/A conversion circuit 4 also includes N-channel MOS transistors 11-13 and inverters 14-16. Offset correction register 3 has three registers 17
~19, and each register 17~19 is a comparator 1.
The bits φ to 2 are stored in accordance with the comparison result from , but before self-correction, all bits are reset to φ in advance. The comparator 1 has three stages of an amplifier circuit 24 consisting of an inverter 20, a MOS transistor 21, and capacitors 22 and 23.
A BAL signal is supplied via 6. The BAL signal becomes "H" when sampling the analog input, and becomes "L" when sampling is completed. 27 and 28 are MOS transistors, which correspond to the switches 5 and 6, respectively. The gates of each MO5I transistor 27 and 28 have an ANIN signal and a D
An AIN signal is applied. The ANIN signal is “H” when sampling the analog input, “L” otherwise, and DAI
The N signal is “H” during correction and comparison, and “L” at other times.
”. To perform self-correction, first register 1 registers 17 to 18
The content of is reset (=φ), the A/D converter is operated to measure the LSB nonlinearity error, and as shown in Figure 7, this error is corrected (in this case, the zero transition voltage is corrected). ), only one of the registers 17 to 19 stores 1'' based on the comparison result of the comparator 1. As a result, the output of the register (for example, 18) that stores 1 is transferred to the inverter 15. The voltage is applied to the gate of the MOS transistor 12 through the resistors Rs and Rh, and the offset voltage on the AVR- side is adjusted. Therefore, when one of the transistors 11, 12, and 13 is turned on, the zero transition voltage is particularly corrected and falls to zero positive silane as shown in FIG. Conventional A/D converters such as these can correct the so-called zero transition voltage, but cannot correct the overall offset from the zero transition voltage to the full-scale transition voltage, and the accuracy of nonlinear error correction is limited. Therefore, it is an object of the present invention to provide an A/D converter that can correct the overall offset voltage and improve the accuracy of nonlinearity error correction. [Means for Solving the Problem] In order to achieve the above object, the A/D converter according to the present invention
A chopper-type comparator with an S transistor compares the analog input with a reference value to determine the MSB of the digital value, and then a successive approximation operation determines the digital value up to the LSB and performs A/D conversion. A: Correcting non-linearity errors in digital values by means of correction
In the /D converter, the offset correction means includes a plurality of charge correction transistors that change the gate capacitance of the MOS transistor in the comparator, and adjusts the charge correction transistor based on a comparison result between the analog input and a reference value. The configuration is such that the gate capacitance of the MO3 transistor is changed by changing the selected number of transistors, and the offset voltage of the comparator is corrected from zero transition to full scale. [Function] In the present invention, a plurality of charge correction transistors are provided to change the gate capacitance of the MOS transistor in the comparator, and the number of selected charge correction transistors is changed based on the comparison result between the analog input and the reference value. Accordingly, the gate capacitance of the MOS transistor can be changed. In this case, M.O.
Since the number of charge correction transistors selected is changed at the timing when the S transistor is turned off, the gate capacitance is appropriately changed and the potential of the node controlled by the MOS transistor is kept constant. Therefore, the potential of the node in the important part of the comparator is calibrated to a constant value, and the offset voltage of the comparator is appropriately corrected from zero transition to full scale, improving the accuracy of nonlinear error correction. do. [Example] The present invention will be described below based on the drawings. 1 to 4 are diagrams showing one embodiment of an A/D converter according to the present invention. FIG. 1 is a block diagram of an A/D converter. In this figure, the difference from the conventional example is that an offset correction circuit 40, which will be described later, is included inside a chopper-type comparator 31, and a D/A conversion circuit. The difference is that the offset correction circuit is removed from 32, and the position of the offset correction register 33 is different. The rest is the same as the conventional example and is given the same reference numeral. FIG. 2 is a circuit diagram of the main part including the offset correction circuit 40. In this figure, the offset correction circuit 40 is composed of N-channel MOS transistors (corresponding to charge correction transistors) 41 to 43 and NOR gates 44 to 46. The sources and drains of the MOS transistors 41 to 43 are all collectively connected to the source side of the MOS transistor 21. One input terminal of NOR gates 44-46 is supplied with signals from registers 47-49, respectively, and the other input terminal is supplied with a BAL signal. Registers 47 to 49 constitute an offset correction register 33, and the stored contents change based on the comparison result from the comparator 31.h 50 is a resistor dollar circuit included in the D/A converter circuit 32, and is connected by resistors RII+R1□. A constant voltage of AVR'' and AVR- is applied to both ends, and a correction reference voltage is taken out from the midpoint of the resistor R+i r R1H. Other components that are the same as those of the conventional example are given the same reference numerals. The offset correction register 33 and the offset correction circuit 40 constitute the offset correction means 51.Next, the operation will be explained, but first the principle of the present invention will be described. In the middle, we focused on the following circuit operation.This can be explained using the conventional timing charts of Fig. 6 and Fig. 3.
In comparator 1, analog input sampling, especially B
When the AL signal becomes "H", the MOS transistor 21 is turned on, and at the end of sampling, the BAL signal becomes "L" and the MOS transistor 21 is turned off. At this time, the charge stored in the capacitor 22 is then compared with the corrected reference voltage and A/D conversion is performed.
OS) As the gate capacitance of the transistor 21 changes, the potential of the node A in the figure decreases (however, the transistor is abbreviated as Tr in the figure). In order to correct this, conventionally the MOS1-transistor 26
When MOS) transistor 21 transitions from on to off, MOSl-transistor 2 is added at the same timing.
6 is switched from off to on. By doing this, the charge discharged from the MOS transistor 21 is absorbed by the -MO3) transistor 26, the potential of the node A is kept constant, and the comparator 1
The comparison operation becomes stable. Among the above operations, the present inventor has discovered that the MOS1 transistor 26
Since the amount of charge compensated for by MO3) is proportional to the gate capacitance of the MO3) transistor 26, the gate area of the MOS transistor 26 is increased.
It has been discovered that the potential to be corrected is determined by increasing the number of . Therefore, in this embodiment, when correcting the nonlinearity error, first, BAL=“H”, DAIN=H”, AN I N
= ``L'' and turn on the switch 29. As a result, the MOS1-transistor 28 is turned on, and a correction reference voltage is sampled from the resistor ladder circuit 50 across the capacitor 22. Next, BAL="L" and DA
IN, , ANIN remain unchanged), registers 47 to 49
The contents of (bit2: bit 1, bit φ) = [
1, 1, 1]. Then, BAL="H3,
The analog input is sampled with DAIN=L and ANIN=“H” and compared with the corrected reference voltage. After that, (bit 2, bit 1, bitφ]-[1,
1, 1] and continues until the comparison result in the comparator 31 is inverted. Then, the inverted values are held in registers 47 to 49, and A/D conversion is executed while holding these values. therefore,

The output of the register holding [0] is BA
When L=“L”, set the Noah gates 44 to 46 (any one or more) to “H” and set the transistors 41 to 4 (MOS)
3 (any one or more) will increase the gate area. As a result, the node A is proportional to the gate area.
The potential at is properly corrected and kept constant, and eventually
In addition to correcting only the zero transition as shown in Figure 4 (a), the offset voltage is also corrected appropriately between the full scale salts as shown in Figure 4 (b), and the overall nonlinearity error is reduced. Correction accuracy can be improved. In the above embodiment, three MOS transistors 41 to 43 and three registers 47 to 49 are provided, but the number is not limited to this and may be any other number. Bye. [Effects of the Invention] According to the present invention, it is possible to self-correct the entire offset voltage from the zero transition voltage to the full-scale voltage, and it is possible to improve the accuracy of correcting nonlinearity errors.

[Brief explanation of drawings]

Figures 1 to 4 are diagrams showing one embodiment of the A/D converter according to the present invention. Figure 1 is a block diagram thereof, Figure 2 is a circuit diagram of its main parts, and Figure 3 is its principle. FIG. 4 is a graph to explain its effect. FIGS. 5 to 7 are diagrams showing a conventional A/D converter, and FIG. 5 is a block diagram thereof. FIG. is a circuit diagram of the main part thereof, and FIG. 7 is a graph for explaining the correction. 2...Successive approximation register, 5.6...Switch, 20...Inverter, 21...MO3I-Range Kuyu, 22.23.
... Capacitor, 24 ... Amplifier circuit, 31 ... Comparator (Chonba type comparator) 32.
...D/A conversion circuit, 33...Offset correction register, 40...
...Offset correction circuit, 41 to 43...
MOS) transistor, 44-46...Nor gate, 47-49...Resistor, 50...Resistance ladder circuit, 51...Offset correction means. lj Timing chart diagram for explaining the principle of one embodiment

Claims (1)

[Claims] A chopper-type comparator having a MOS transistor compares the analog input with a reference value to determine the MSB of the digital value.
In the A/D converter which determines the digital value up to LSB by successive approximation operation and performs A/D conversion, and corrects the non-linearity error of the digital value by offset correction means, the offset correction is performed. The means includes a plurality of charge correction transistors that change the gate capacitance of the MOS transistor in the comparator, and changes the selected number of the charge correction transistors based on the comparison result between the analog input and a reference value to adjust the number of the MOS transistors. An A/D converter characterized in that the gate capacitance is changed to correct the offset voltage of a comparator from zero transition to full scale.