JPH0224721A - Program controller - Google Patents

Abstract

PURPOSE:To remove useless time in jump operation by providing the title device with two program counters and two instruction registers. CONSTITUTION:An instruction is read out from a program memory 10 under control based upon the a 1st program counter 11a, stored in a 1st instruction register 13a and decoded by a decoder 15. When a jump instruction is stored in the register 13a, an address to be jumped is stored in a 2nd program counter 11b through a jumped address transfer line 17a simultaneously with the start of instruction decoding based upon a decoder 15. After decoding the jump instruction by the decoder 15, a selector 14 is switched by a selection control circuit 16 and the output of a 2nd instruction register 13b is outputted to the decoder 15.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program control device provided inside a digital signal processor (DSP).

(Prior Art) Digital signal processing processors are used in speech synthesis devices, digital filters, and the like in order to calculate processing data at high speed.

The operating program of this digital signal processing processor is either built into the processor or stored in an external program memory. - In general, instructions constituting a program are sequentially stored in a program memory in the order of execution. However, since programs for digital signal processors often repeat the same instructions, a program control device that dynamically reads instructions is provided in order to reduce the capacity of the program memory.

FIG. 2 shows a block diagram of such a conventional program control device.

This device reads instructions constituting a program stored in a program memory 1 in a predetermined order to obtain a decode instruction 2, which is output to an external circuit.

This device includes a program counter 3 that controls reading of instructions from the program memory 1, an instruction register 4 that temporarily stores instructions read from the program memory 1, and an instruction register 4 that decodes instructions stored in the instruction register 4. The device is comprised of a decoder 5 which outputs a decode instruction 2, and a controller 6 which controls the operation of each part of this device.

The program counter 3 is a counter that determines the read address of the program memory 1, and is normally controlled to count up by 1 every machine cycle, for example. Instructions are read from the program memory 1 from the corresponding address under the control of the program counter 3 and stored in the instruction register 4.

The instructions stored in the instruction register 4 are decoded by the decoder 5. The instructions typically include arithmetic instructions, jump instructions, I10 instructions, and the like. In the case of an instruction other than a jump instruction, once decoding is completed by the decoder 5, the decoding instruction 2 is sent as is.
is output to the external circuit as .

In the case of an instruction other than a jump instruction, the controller 6 instructs the program counter 3 to count up, and instructs the instruction register 4 to store the next instruction output from the program memory 1.

On the other hand, in the case of a jump instruction, the decoder 5 transfers the jump destination address included in the instruction to the program counter 3, and instructs the program counter 3 to store the jump destination address. by this,
The program counter 3 starts counting up by 1 again with the jump destination address as the starting point, and the program memory 1 outputs a corresponding instruction.

Incidentally, reading instructions from the program memory 1 usually requires a certain access time.

Furthermore, when the decoder 5 decodes the instructions stored in the instruction register 4, a certain decoding time is still required.

Therefore, the program counter 3 outputs a predetermined address signal to the program memory 1, an instruction is read from the program memory 1 in response to the kneading, the instruction is stored in the instruction register 4, and the decoder 5 A certain amount of operating time is required to decipher the code.

There is no problem if the calculation speed of the external circuit that receives the decode instruction 2 output by this program control device is slower than the above operation time, but conversely, if the calculation speed is increased, the decode instruction 2 The slow output of is a factor that prevents speeding up of calculations.

Therefore, conventionally, the reading of instructions from the program memory 1 and the decoding of instructions by the decoder 5 are executed in parallel by so-called vibe line control. That is,
While the program counter 3 supplies an address signal to the program memory 1 and an instruction is read out, the decoder 5 receives the instruction read out one machine cycle before from the instruction register 4 and executes the decoding operation.

In conventional program control devices, the processing speed has been increased in this way.

(Problems to be Solved by the Invention) Now, the operation of the conventional program control device as described above regarding a jump instruction will be explained.

FIG. 3 is an operation time chart of the conventional device.

As shown in Figure (a), the program counter is incremented by 1 in the order of m-1, m, m+1 every machine cycle. Then, the instructions read out corresponding to the address signals are sent to C knee 2 and C knee 2, respectively.
When displayed as Ct-+..., the instruction is stored in the instruction register as shown in FIG. 3(b), and is decoded by the decoder as shown in FIG. 3(C).

First, as shown in FIG. 3, when the program counter 3 indicates m-1, the instruction register 4 contains the following information:
Instruction Cm- which was already read out one machine cycle ago
2 is stored and decoded by the decoder 5.

When the program counter 3 is counted up by 1 and the address signal becomes m, the instruction cm-t is stored in the instruction register 4 and decoded by the decoder 5. It is assumed that the instruction C1 is a jump instruction, and that the jump instruction includes a jump destination address.

Whether it is a jump instruction or not is known only after the decoder 5 finishes decoding the instruction. Therefore, by the time the jump destination address β included in the instructions C and n is stored in the program counter 3, the program counter has already reached m+1. , and an instruction C+a+1 (not shown) is read out.

Since this instruction Cm*1 is an unnecessary instruction, the operation of the device is overlooked for one machine cycle.

Then, the program counter increases by +1 with the address signal.
When outputting, instruction C4 is stored in the instruction register,
This is decoded by the decoder 5. Thereafter, the program counter is incremented to g+2, and the same operations as already described are continued.

In other words, conventionally, when a jump instruction exists in a program, one machine cycle worth of wasted time always occurs.Therefore, for example, there is a lot of processing such as classification and search, that is, there are a large number of jump instructions. In programs, there is a problem in that this dead time occupies a large proportion of the execution time, reducing processing efficiency.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a program control device that can eliminate wasted time in jump operations and perform efficient control.

(Means for Solving the Problems) A program control device of the present invention reads out and decodes instructions constituting a program from a dual-port program memory storing a program in a predetermined order, and outputs the instructions to an external circuit. In a program control device that
a first program counter and a second program counter that control reading of the instructions from the program memory; A first instruction register is connected to a second output port of the program memory and temporarily stores instructions read from the program memory under the control of the second program counter. a second instruction register for storing instructions; a decoder for decoding instructions stored in any of the instruction registers; a first output port of the program memory and the second program counter; selectively controlling the instruction register so that the decoder decodes an instruction stored in either one of the jump destination address transfer line connecting the second output port and the first program counter and the instruction register; , and a selection control circuit that switches the selection of the instruction register at the next timing when a jump instruction is stored in the selected instruction register.

Further, the same thing can be done by using two program memories storing two identical programs.

(Operation) The above device usually reads an instruction from a program memory under the control of a first program counter, stores it in a first instruction register, and a decoder decodes the instruction stored there. It operates to do the following. If there is no jump instruction and the program counter is counted up one by one to read instructions, this operation is repeated.

On the other hand, when a jump instruction is stored in the first instruction register, at the same time that the decoder starts decoding the jump instruction, the jump destination address in the jump instruction is transferred to the second program counter via the jump destination address transfer line. is stored in

Then, when the decoder finishes decoding the instruction stored in the first instruction register and recognizes it as a jump instruction, the selection control circuit immediately outputs the output of the second instruction register to the decoder. Switch that selection.

The second instruction register has already stored the instruction read based on the jump destination address of the second program counter, and the decoder immediately starts decoding that instruction. As a result, jump instructions do not cause wasted time as in the conventional case.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of a program control device of the present invention.

This device includes a program memory 10, a first program counter lla and a second program counter lla for controlling reading of instructions from the program memory 10.
b, a first instruction register 13a that stores instructions read from the program memory 10, a second instruction register 13b, and a selector 14 that selects the outputs thereof;
A decoder 15 and a controller 16 that controls the operation of each part.
It has

The first program counter lla and the second program counter llb are both configured to count up by one under the control of the selection control circuit 16, or to store a jump destination address.

Further, the first instruction register 13a is connected to the program memory 1.
o's first output port. Further, the second instruction register 13b is connected to the second output port 12b of the program memory 10.

The program memory 10 is a so-called dual-port memory, in which instructions read under the control of the first program counter lla are output to the first output port 12a, and instructions read under the control of the second program counter llb. The issued command is output to the second output port 12b. As is well known, in this dual port memory, if the address signals input from the two program counters lla and llb do not match, the instructions stored therein are read out separately and in parallel. consists of random access memory.

The selector 14 is a circuit that selects either one of the instructions output from the first instruction register 13a or the second instruction register 13b and outputs the selected instruction to the decoder 15.

The selection operation of the selector 14 is controlled by a selection control circuit 16. The decoder 15 is a circuit that decodes the command output from the selector 14 and outputs the decoded command to an external circuit (not shown). The selection control circuit 18 is
It consists of a gate circuit that controls the operations of program counters lla and llb and the selection operation of the selector 14 according to the contents of the instructions decoded by the decoder 15.

Furthermore, this circuit includes a jump destination address transfer line 17a connecting the first output port 12a of the program memory 10 and the second program counter llb, and a second output port 12b of the program memory 10. 1st
A jump destination address transfer line 17b is provided which connects the program counter lla of the jump destination address transfer line 17b. These jump destination address transfer lines 17a and 17b unconditionally transfer a portion of the instruction read from the program memory 10 corresponding to the jump destination address to the first program counter lla or the second program counter llb.
It is a parallel transfer line that transfers data to For example, the first
An instruction is read from the program memory 10 under the control of the program counter 11a of the first output port 12.
When a process is executed based on an instruction output from a, a portion corresponding to the jump destination address of that instruction is always stored in the second program counter. The selection control circuit 16 thus controls the operation of each section.

The program control device of the present invention having the above configuration operates as follows.

FIG. 4 is a time chart illustrating the present invention in detail.

In this embodiment, it is assumed that processing is executed based on instructions read out under the control of the first program counter lla shown in FIG.

That is, as shown in FIG. 4(a), first, the first program counter lla is set to m-1,
The count continues as m, m+1, and so on. Then, as shown in FIG. 4(b), instructions C--2, C-re, Cm are applied to the first instruction register 13a, one machine cycle later than the count timing of the program counter 3. Instructions are stored and decoded by the decoder 15 [FIG. 4(f)].

At this time, the second program counter llb stores the portion of the instruction read from the program memory 10 that corresponds to the jump destination address, but instructions other than the jump instruction are stored in the second program counter llb. When read, the data is meaningless and as shown in FIGS. 4(c) and (d)
It is completely ignored as shown in . That is, as shown in FIG. 4(e), the selector selects to output only the a side, that is, the output of the first instruction register 13a, to the decoder 15.

Here, it is assumed that the first program counter lla has a count of m, and one machine cycle later, a jump instruction C1 is stored in the first instruction register.

In this case, the jump destination address °C is stored in the second program counter llb. At this timing, the selector 14 is still selecting the a side, that is, the first instruction register 13a, and the decoder 15 is decoding the instruction C1. Then, when this instruction C1 is decoded,
Since this is a jump command, the selection control circuit 16 controls the selector 14 and switches the selection to the b side [4th
Figure (e)].

On the other hand, the second program counter llb has already
Jump destination address 2 is indicated before the machine cycle, and the corresponding instruction is read out from the program memory 10 to the second instruction register 13b [Fig. 4(d)
)]. The timing at which this is read is the previous jump instruction C.

Immediately after it is decoded. At that stage, the selector has been switched to the b side, and the jump destination address is ℃
The instruction CQ stored in the decoder 15 is decoded by the decoder 15. Thereafter, instructions are sequentially read from the program memory 10 under the control of the second program counter llb and used for processing.

The subsequent operations are similar to those described above.

As you can see from the operation in Figure 4, jump command C
, , is executed, there is no wasted time equivalent to one machine cycle as in the conventional case. Therefore, when executing a program that includes many jump instructions, processing can be executed with high efficiency without wasting time.

In the embodiment shown in FIG. 1, a dual port memory is used to read the program. Since this program memory is a random access memory, for example, while the first program counter lla reads an instruction and executes a predetermined process, the second program counter llb is used to read an instruction from an arbitrary address. New instructions can be written to. As a result, it becomes possible to rewrite the program as and when necessary and execute more sophisticated and complex processing.

FIG. 5 shows a block diagram of the main parts of another embodiment of the device of the present invention.

In this device, the program memory 10 in the device shown in FIG. 1 is replaced by two program memories.

That is, as shown in the figure, the first program memory 10'a
and a second program memory 10'b. It is assumed that both of these memories are, for example, read-only memories in which exactly the same program is stored.

In this way, it is possible to perform exactly the same operation as the device shown in FIG. Moreover, even if two read-only memories with the same contents are used, due to the structure of the read-only memory, the hardware
It is possible to achieve a smaller size than the embodiment of FIG.

In addition, in this example, regarding other connections etc.
It is completely the same as FIG. 1, and its illustration and explanation will be omitted.

The present invention is not limited to the above embodiments.

In the embodiment shown in FIG. 1, it has been explained that the selection control circuit 16 controls the selector 14 inserted between the instruction registers 13a and 13b and the decoder 15. Various modifications are possible, such as directly controlling the output, providing two input ports for the decoder 15, and controlling the selection of which port inputs an instruction to be processed. Furthermore, the operation control of the program counter can also be replaced with known equivalent control means.

(Effects of the Invention) According to the program control device of the present invention described above, two
One program counter and two instruction registers are provided, and while an instruction stored in one instruction register is being decoded, a jump destination address is specified by the other program counter, and the jump destination address is specified at the same time as the jump instruction is decoded. Since it is possible to output instructions, it is difficult to waste time when executing jump instructions, as is the case with conventional methods, and highly efficient and high-speed program control is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the program control device of the present invention, FIG. 2 is a block diagram showing an example of a conventional program control device, FIG. 3 is a time chart showing the operation of the conventional device, and FIG. The figure is a time chart showing the operation of the present invention, and FIG. 5 is a main part block diagram showing another embodiment of the apparatus of the present invention. 10...Program memory, 10'a...First program memory, 10'b.
...Second program memory, 11a...First program counter, 11b...Second program counter, 12a...First output port, 12b...Second output port, 13a. ...First instruction register, 13b...Second instruction register, 14...Selector, 15...Decoder, 16...Selection control circuit. Patent Applicant: Oki Electric Industry Co., Ltd. Procedural Amendment Document Date: February 6, 1989

Claims (1)

[Scope of Claims] 1. A program control device that reads and decodes instructions constituting a program from a dual-port program memory storing a program in a predetermined order and outputs the commands to an external circuit, wherein the program memory a first program counter and a second program counter for controlling reading of the instructions from the program memory; and a first program counter connected to a first output port of the program memory;
a first instruction register that temporarily stores instructions read from the program memory under control of the first program counter; and a second instruction register connected to a second output port of the program memory;
a second instruction register that temporarily stores instructions read out from the program memory under control of the second program counter; a decoder that decodes the instructions stored in either of the instruction registers; and the program memory. a jump destination address transfer line connecting the first output port of the controller and the second program counter, and connecting the jump destination address transfer line connecting the second output port and the first program counter, and one of the instruction register. a selection control circuit that selectively controls the instruction register so that the decoder decodes the stored instruction, and switches the selection of the instruction register at the next timing when a jump instruction is stored in the currently selected instruction register; A program control circuit characterized by comprising: 2. A program control device that reads instructions constituting the program from a first program memory and a second program memory each storing the same program in a predetermined order and outputs the commands to an external circuit, a first program counter that controls reading of the instructions from the program memory; a second program counter that controls reading of the instructions from the second program memory; and by control of the first program counter. a first instruction register that temporarily stores instructions read from the first program memory; and a second instruction register that temporarily stores instructions read from the second program memory under control of the second program counter. a decoder for decoding the instructions stored in any of the instruction registers; a decoder connecting the output port of the first program memory and the second program counter, and connecting the output port of the first program memory to the second program counter; a jump destination address transfer line connecting the output port of the first program counter with the first program counter; and selectively controlling the instruction register so that the decoder decodes the instruction stored in either one of the instruction registers; A program control circuit further comprising: a selection control circuit that switches the selection of the instruction register at the next timing when a jump instruction is stored in the selected instruction register.