JPH0224749A - Memory data writing accelerating device - Google Patents

Abstract

PURPOSE:To shorten a data writing time in a main storage device capable of executing portion specification writing by providing the title device with a means for converting a writing portion specification in the main storage device into a whole portion specification and outputting the converted instruction. CONSTITUTION:The same data as a part of data stored in the main storage device 2 are stored in the same address of a buffer storage device 100. A writing portion instruction for instruction a writing portion in a data writing unit of the main storage device 2 is inputted by a writing portion instruction conversion part 200 and the writing portion instruction is converted into a whole portion instruction for instructing the whole parts of the data writing unit based on a bit signal HT outputted from the storage device 100 and the converted instruction is outputted to the main storage device 2. The data of the data writing unit are edited from writing data and data stored in the memory of the storage part 100 corresponding to a specified address by a writing data editing part 300 and the edited data are outputted to the main storage device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device for speeding up data writing to the memory of the main storage device in a data processing system that performs site-specific writing to the main storage device. It is.

(Prior Art) Conventionally, a data processing system includes a main memory, and data is stored in the main memory.

If the main storage device is capable of site-specific writing, input a signal instructing the writing portion within the data writing unit of the main storage device, the write data, and the address of the memory that stores the write data. A check bit is added to the data and written to the memory.

The instruction for the write part in the data write unit includes an all-parts instruction (indicating all parts of the data write unit).
There are two types: a full write instruction (hereinafter referred to as a full write instruction) and a partial site instruction (hereinafter referred to as a partial write instruction) that specifies a part of the data write unit.

Further, some data processing systems of this type are equipped with a buffer storage device to compensate for differences in data flow speed between components.

(Problem to be Solved by the Invention) However, in the above-mentioned main storage device that allows site-specific writing, when a full write instruction is received, a check bit is simply added to the input write data and written to the memory. However, when receiving a partial write instruction, it first reads the data stored in the memory at the specified address and checks whether the data is normal or not based on the check bit added to the data. Make a judgment. As a result of the determination, if the data is normal, the input write data and read data are edited to create write data to the memory. Furthermore, since the data is written into the memory after the check bits are added to the data, there is a problem that it takes time.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a device capable of shortening the time required to write data to a main storage device in which site-specific writing is possible.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides for storing data that is the same as at least a part of the data stored in the main memory at the same address as the address in the main memory. a memory unit that outputs a hit signal indicating whether or not data is stored in the memory at a designated address; and a storage unit that designates a write portion within a data write unit of the main memory When a write site instruction is input and data is stored in the memory based on the hit signal, the write site instruction is converted into an all site instruction that specifies all parts of the data write unit, and the main a writing part instruction conversion unit that outputs the writing part instruction to the main storage device when the data is not stored in the memory; A write operation in which the data in the data write unit is edited from the write data and the data stored in the memory of the storage unit corresponding to the specified address and output to the main storage device. A memory data writing acceleration device consisting of a data editing section was constructed.

(Function) According to the present invention, the storage unit stores at least part of the data stored in the main storage device in the memory at the same address as the address in the main storage device, and A hit signal indicating whether data is stored in the memory at the specified address is output. Further, the write site instruction conversion section inputs a write site instruction that specifies a write section within a data write unit of the main storage device, and based on the hit signal, the memory of the storage section corresponding to the specified address is input. When data is stored in the memory, the write part instruction is converted into an all part instruction that specifies all parts of the data write unit and is output to the main storage device, and no data is stored in the memory. At this time, the write location instruction is output to the main storage device. Further, the writing data editing section inputs the writing part instruction and the writing data corresponding to the writing part instruction, and the writing data and the data stored in the memory of the storage part corresponding to the designated address are combined. The data in the data writing unit is edited and output to the main storage device.

(Example) FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a central processing unit, 2 is a main storage device, and 3 is a memory data write acceleration device.

When the central processing unit 1 writes write data WDI to WD4 consisting of 16 bits to the main storage device 2, the central processing unit 1 writes the write data WD1 to WD4 and the write data WDI to WDI to the main storage device 2.
It outputs an address signal AD indicating the address of the memory storing WD4, and write site instruction signals WPI to WP4 indicating the write portion within the data write unit of the main memory device 2.

The main memory device 2 stores write data WTDI to WTD4 consisting of 16 bits and write data WTDI to WT.
Address signal A indicating the address of the memory storing D4
D, write site instruction signals WS1 to W34 that instruct the write portion within the data write unit, and the like are input to write data to the memory. In the main memory device 2, the data write unit is 16 bits, and the data write unit is further divided into write locations of 4 bits each. The write site instruction signals WS1 to WS4 are composed of 4 bits, each of which corresponds to the write site, and the write site instruction signals WS1 to WS4 are set to logic "1".
1, data is written to the write site corresponding to the write site instruction signals WSI to WS4. When the write site instruction signals WS1 to WS4 are at logic '0'', the data stored in the write site corresponding to the write site instruction signals WSI to WS4 is saved as is.

The memory data write acceleration device 3 includes a buffer storage device 100 as a storage section, and a write location instruction conversion section 20.
0 and a write data editing section 300.

The buffer storage device 100 is generally known and is a storage device used to compensate for differences in data flow rates between components of a data processing system or for the time of occurrence of events between components. be. The buffer storage device 100 has a memory for storing at least a part of the data stored in the main storage device 2 at the same address as the address in the main storage device 2. The 16-bit held data MDI to MD4 stored in the memory at the specified address is output. It also outputs a hit signal HT indicating whether data is stored in the memory at the designated address. The hit signal HT becomes logic '1' when data is stored in the memory.

The writing site instruction conversion section 200 is composed of a four-man powered OR circuit 211, a two-man powered AND circuit 221, and two-man powered OR circuits 231 to 234. The OR circuit 2
Writing site instruction signals WPI to WP4 outputted from the central processing unit 1 are connected to the four manual input terminals 11, and the OR
The output signal W of the circuit 211 is connected to one input of the AND circuit 221. In addition, the AND circuit 221
A hit signal HT output from the buffer storage device 100 is connected to the other input of the buffer storage device 100 .

The output signal A of the AND circuit 221 is connected to one input of each of the OR circuits 231 to 234. Further, the first bit WP 1 of the write site instruction signal is input to the other input of the OR circuit 231.
The other input of 2 is the second bit W of the writing site instruction signal.
The other input of the OR circuit 233 is connected to the third bit WP3 of the write site instruction signal, and the other input of the OR circuit 234 is connected to the fourth bit WF2 of the write site instruction signal. The respective output signals WS1 to WS4 of the OR circuits 231 to 234 are connected to the main storage device 2 as write site instruction signals.

In the write site instruction converter 200, when at least one bit of the input write site instruction signals WPI to WP4 is logic "1", the output signal W of the OR circuit 211 becomes logic "1", and When the hit signal HT is logic "1", the output signal A of the AND circuit 221 becomes logic "1". As a result, OR circuits 231 to 23
All of the output signals WS1 to WS4 of 4 become logic "1".

Further, when the hit signal HT is at logic "0", the output signal A of the AND circuit 221 becomes logic "0", and the output signals WS1 to WS4 of the OR circuits 231 to 234 are equal to the write instruction signal WPI. ~It will be the same as WP4.

The write data editing section 300 includes NOT circuits 311 to
314, a 4-man OR circuit 321, a 2-man AND circuit 331 to 334, and a tri-state output bus driver 3
41 to 348. The bus drivers 341 to 348 each have a 4-bit input/output and an output control terminal, and when a logic '1' signal is input to the output control terminal, each of the bus drivers 341 to 348 receives an input signal. is output, and when a logic “0” signal is input to the control terminal, the bus drivers 341 to 3
The output of 48 becomes high impedance.

The input of the N07 circuit 311 is the first bit WPI of the write site instruction signal, the input of the N07 circuit 312 is the second bit WP2 of the write site instruction signal, and the input of the N07 circuit 313 is the write site instruction signal. The third bit WP3 of the part instruction signal is connected to the input of the N07 circuit 314, and the fourth bit WP4 of the write part instruction signal is connected to the input of the N07 circuit 314, respectively.

The four inputs of the OR circuit 321 are connected to the write site instruction signals WPI to WP4, and the OR circuit 321
The output signal B is connected to one input of each of the AND circuits 331 to 334. The AND circuit 3
The other input of the AND circuit 332 is the output of the N07 circuit 311, and the other input of the AND circuit 332 is the output of the N07 circuit 311.
The other input of the AND circuit 333 is connected to the output of the N07 circuit 313, and the other input of the AND circuit 334 is connected to the output of the N07 circuit 314. Further, the output of the AND circuit 331 is connected to the output control terminal of the bus driver 345, the output of the AND circuit 332 is connected to the output control terminal of the bus driver 346, and the output of the AND circuit 333 is connected to the output control terminal of the bus driver 345.
The output of the AND circuit 334 is connected to the output control terminal of the bus driver 348, and the output of the AND circuit 334 is connected to the output control terminal of the bus driver 348.

The output control terminal of the bus driver 341 receives the first bit WPI of the write location instruction signal, the output control terminal of the bus driver 342 receives the second bit WP2 of the write location instruction signal, and the output of the bus driver 343 receives the first bit WPI of the write location instruction signal. The third bit WF2 of the write site instruction signal is connected to the control terminal, and the fourth bit WP4 of the write site instruction signal is connected to the output control terminal of the bus driver 344.

The input of the bus driver 341 includes the central processing unit 1.
The first 4 bits WD1 of the write data output from the bus driver 342 are input to the bus driver 342, and the third 4 bits WD2 of the write data are input to the input of the bus driver 343. 4-bit WD3 is
The fourth 4-bit WD4 of the write data is connected to the input of the bus driver 344, respectively. Output signals WTDI to WT of the bus drivers 341 to 344
D4 is connected to the buffer storage device 100 and is manually input to the main storage device 2 as write data.

The input of the bus driver 345 receives the first four bits M of the held data output from the buffer storage device 100.
DI is input to the bus driver 346, and the second 4-bit MD2 of the held data is input to the bus driver 346.
The third 4-bit MD3 of the held data is connected to the input of the bus driver 348, and the fourth 4-bit MD4 of the held data is connected to the input of the bus driver 348. Further, 4 bits of the output of the bus driver 345 are connected to 4 bits of the output of the bus driver 341, 4 bits of the output of the bus driver 346 are connected to 4 bits of the output of the bus driver 342, and 4 bits of the output of the bus driver 347 are connected to the 4 bits of the output of the bus driver 345. 4 of the output of
The bits are 4 bits of the output of the bus driver 343,
The four bits of the output of the bus driver 348 are connected to the four bits of the output of the bus driver 344, respectively.

The write data editing section 300 processes the write part instruction signals wP1 to WP4 input from the central processing unit 1.
The bus driver 3 corresponds to the bit that is logic “1”
The central processing unit 1 via any one of 41 to 344
The write data WDI to WD4 inputted from the main storage device 2 are output to the main storage device 2. Further, the writing site instruction signal WP
The data MDI to MD4 held in the buffer storage device 100 is output to the main storage device 2 via one of the bus drivers 345 to 348 corresponding to the bit of logic "0#" of I to WP4.

Further, an address signal AD indicating the address of a memory storing write data WD1 to WD4 outputted from the central processing unit 1 is connected to the main storage device 2, and
It is connected to the buffer storage device 100 .

Next, the operation of this embodiment will be explained based on an example of data shown in FIG.

When the central processing unit 1 performs a partial write to rewrite the upper byte of data stored in the memory at a predetermined address of the main storage device 2 to AB (hexadecimal), the 1 4-bit WD
1 has A (hexadecimal number), second 4-bit WD2 has B
(hexadecimal number) is the third and fourth 4-bit WD3. W.D.
Indeterminate data is output to 4, respectively. Further, the first bit WPI and the second bit W of the write site instruction signal
A logic "1" signal is output to P2, and a logic "0" signal is output to the third bit WP3 and fourth bit WP4.At this time, the main memory device 2 and the buffer memory device 1
1234 (hexadecimal) in the memory at the corresponding address of 00
, the hit signal HT output from the buffer storage device 100 is a logic '1'''.
become. As a result, the write site instruction signal WSI~ is output from the write site instruction converter 200 to the main storage device 2.
All four bits of WS4 become logic "1", which is converted into a full write instruction and output.

The write data editing unit 300 extracts 1 as the first 4-bit MDI of the retained data from the buffer storage device 100.
(hexadecimal number) as the second 4-bit MD2 2 (16
3 (hexadecimal) as the third 4-bit MD3
and input 4 (hexadecimal number) as the fourth 4-bit MD4.

As a result, the output signal B of the OR circuit 321 becomes the logic a1''
At the same time, through each of the bus drivers 341 and 342, the upper bytes of the write data output from the central processing unit 1, that is, the first 4 bits WDI and the second 4 bits WD2 of the write data are , is output to the main storage device 2 and the buffer storage device 100. At this time, the output of the bus driver/<343.344 is in high impedance.

One input signal B of each of the AND circuits 331 to 334 has a logic of "1 degree," and the other input signal indicates that the write site instruction signals WPI to WP4 correspond to the NOT circuit 31.
This is a signal inverted by 1 to 314. Therefore, AND
The output signals of circuits 331 and 332 become logic “0” and A
The output signals of the ND circuits 333 and 334 become logic "1". As a result, the lower bytes of the held data output from the buffer storage device 100, that is, the third 4 bits MD3 and the fourth 4 bits MD4 of the held data, are transferred to the main memory via the bus drivers 347 and 348, respectively. Device 2
and is output to the buffer storage device 100. At this time,
The outputs of the bus drivers 331 and 332 are high impedance.

Therefore, the first 4 bits WT of the write data output from the write data editing section 300 to the main storage device 2
DI becomes A (hexadecimal number) and the second 4-bit WTD2
becomes B (hexadecimal), and the third 4-bit WTD3 becomes 3
(hexadecimal number), and the fourth 4-bit WTD4 is 4 (1
Hexadecimal).

Further, the write data WTDI to WTD4 are written to the memory of the main storage device 2 and also written to the memory of the buffer storage device 100.

As a result, the data stored in the memory of the buffer storage device 100 is also updated.

In this way, the main storage device 2 has received the full write instruction, and the input write data WTDI to WT
All that is required is to add a check bit to D4 and write it into memory.

In this embodiment, the storage section is configured using a buffer storage device, but the same effect can be obtained even if the storage section is configured separately from the buffer storage device.

(Effects of the Invention) As explained above, according to the present invention, data that is the same as at least a part of the data stored in the main memory is stored at the same address as the address in the main memory. A storage unit that includes a memory and outputs a hit signal indicating whether data is stored in the memory at a designated address, and inputs a write location instruction that designates a write portion within a data write unit of the main storage device. When data is stored in the memory based on the hit signal, the write part instruction is converted into an all part instruction that specifies all parts of the data write unit and output to the main storage device. , when no data is stored in the memory, a write site instruction converter outputs the write site instruction to the main storage device, and inputs the write site instruction and write data corresponding to the write site instruction. , a write data editing unit that edits the data in the data write unit from the write data and the data stored in the memory of the storage unit corresponding to the designated address, and outputs the edited data to the main storage device; Since the write speed-up device is configured, when data is written by specifying a part to a main storage device that allows part-specified writing, the data is stored in the memory of the storage unit corresponding to the specified address. When the write part instruction for the main storage device is converted into an all-part instruction, the write data corresponding to the all-part instruction is edited and output to the main storage device. Therefore, data is written in the main memory by specifying all parts, which requires no write processing time, and there is an advantage that the time required to write data to the main memory can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of data. 1...Central processing unit, 2...Main storage device, 3...
Memory data write acceleration device, 100... Buffer storage device (storage unit), 200... Write site instruction conversion unit, 211... OR circuit, 221... AND circuit,
231-234...OR circuit, 300...Write data editing section, 311...314...NOT circuit, 3
21...OR circuit, 33-334...AND circuit,
341-348... Tri-state bus driver. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Yoshi 1) Sei Takashi Ira 11ΣHo 1 Figure 2 WJ

Claims (1)

[Scope of Claims] A memory at a specified address, including a memory storing at least part of the same data stored in a main memory at the same address as the address in the main memory. a storage unit that outputs a hit signal indicating whether or not data is stored in the main storage device; and a storage unit that inputs a write location instruction that designates a write portion in a data write unit of the main storage device, and inputs a write location instruction that specifies a write portion in a data write unit of the main storage device, and stores the data in the memory based on the hit signal. when data is stored in the data write unit, converting the write part instruction into an all part instruction indicating all parts of the data write unit and outputting it to the main storage device;
When no data is stored in the memory, a write site instruction converter outputs the write site instruction to the main storage device; inputs the write site instruction and write data corresponding to the write site instruction; and a write data editing unit that edits the data in the data write unit from the write data and the data stored in the memory of the storage unit corresponding to the designated address, and outputs the edited data to the main storage device. Features a memory data writing speed-up device.