JPH0225036A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device at high speed.
MOS that can support high integration and has excellent α-ray resistance
The present invention relates to a method for manufacturing a transistor.

[Prior art] Single-crystal silicon (S.
A device structure having an active region in a film has been proposed. In particular, the element structure in which the source and drain of a MOS transistor are formed on an insulating film (hereinafter referred to as S/D-3OI MO
Compared to the conventional device structure in which the source and drain are not on an insulating film, the device can reduce stray capacitance and increase the speed of the device. It has the advantage of being able to reduce soft errors caused by alpha rays. S/D-8○ Engineering Even compared to the device structure created in a single crystal silicon film in which the active region including the channel region of a MOS transistor is entirely formed on an insulating film, The device has the following advantages: (1) the device can be formed in the area with the best crystallinity around the seed portion (hereinafter referred to as the “seed portion”); and (1) the substrate potential of the device can be controlled because the seed portion contacts the substrate. Regarding dRAM cells using this device, please refer to IE Technical Digest (19
1987) pages 344 to 347 (IEEE, T
mechanical Digest (1987) p p
344-347). The switching MOS transistor in the dRAM cell is an S/D-SOI Mo5, and the manufacturing method for this element is as follows. j) Form an oxide film on the surface of the silicon substrate by normal thermal oxidation. ii) An opening in the oxide film is formed in a region that will become the gate of the device, and silicon is selectively grown using the opening as a seed. 1ii) In selective growth, lateral single crystal silicon is obtained from the seed overhanging the oxide film, so the film thickness on the seed is thicker than that on the oxide film. Therefore, the surface of the sample is polished and the thickness of the single crystal silicon oxide film is processed to a desired thickness. iv) Form a gate electrode on the seed using a normal polycrystalline silicon gate formation process 6) Using the gate as a mask, ion implantation is performed for the source and drain to form a MoS transistor. Problem M1 to be Solved by the Invention In the above-mentioned conventional S/D-3○ method for manufacturing a MOS transistor, the accuracy of alignment between the seed pattern and the gate pattern depends on the alignment accuracy of lithography. If the matching between the seed layer and the gate layer is not good, the impurity region of the source or drain will invade into the seed, and a depletion region will be formed in the substrate when the device is operated, increasing stray capacitance. As a result, the operating speed of the element becomes slower. Furthermore, if a depletion region is formed within the substrate, it may cause errors due to alpha rays. Therefore, when forming this element structure, in order to take advantage of the effects of operating speed and reducing soft errors caused by alpha rays, even if the element is miniaturized, it is necessary to
It is necessary to carry out an element formation process that fully takes into account the consistency between the seed pattern and the gate pattern. SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method for producing S/D-80 MOS transistors with high yield, which reduces device operating speed and soft errors caused by alpha rays. [Means for Solving the Problems 1] The above purpose is to form a gate pattern and then implant oxygen ions using the gate pattern as a mask, in order to obtain consistency between the seed pattern and the gate pattern. A buried oxide film is formed directly under the drain formation region. This is then achieved by again implanting impurities to form the source and drain using the gate pattern as a mask. [Operation 1] The gate pattern previously formed on the oxide film is used as a mask for oxygen ion implantation for forming an insulating film directly under the source and drain, and for impurity ion implantation for forming the source and drain. Thereby, the seed portion is formed in self-alignment with the gate pattern. Therefore, the S/D-SOI MOS transistor can be formed by a highly reliable manufacturing process that is compatible with miniaturization and has a good yield. [Example] The present invention will be described in detail below. <Example 1> First, a p-type crystal silicon (100) substrate 1 was
' C heat treatment for 20 minutes in an oxygen atmosphere, approximately 25 nm
An oxide film 2 was formed. After that, B for Vch control
+ ions 3 were implanted (see Figure 1a). Next, a polycrystalline silicon film 4 doped with phosphorus (P) of about 10''/cm3 was deposited to a thickness of about 0.4 μm (see Figure 1). A gate 5 of polycrystalline silicon was formed by dry etching using gas. Oxygen ions 7 were implanted (160" + 150 K e) with the photoresist pattern 6 used for gate processing remaining.
V r 2
reference). Thereafter, the photoresist pattern 6 was removed in oxygen plasma. Furthermore, As ions 9 were implanted (80KeV
, 5×10"a!1-") to form a source 1o and a drain 11 (first, see FIG. d). Next, the elements were separated. A photoresist pattern 12 is formed in the element formation region, and the polycrystalline silicon outside the resist pattern is removed using dry etching conditions with a high etching ratio of silicon to oxide film, and then the oxide film is removed using an aqueous solution of hydrofluoric acid. Then, the silicon substrate 1 above the oxide film 8 formed by ion implantation was etched away by dry etching (see FIG. 1C). Thereafter, the photoresist pattern 12 was removed, and a contact hole 14 for wiring connection was formed in the P-doped CVD oxide film 13 deposited as an interlayer insulating film. In particular, the contact hole of the gate 5 was made larger than the gate pattern in order to increase the contact area. Finally, A1 wiring 1 is formed by depositing AI and patterning it.
5 was formed to create an S/D-3OI MOS transistor (see Figure 1 f and g, where g is the same @f).
). S/D of this example formed by the above manufacturing process
- In the SOI MOS transistor, the oxide film layer 8 is formed inside the substrate by oxygen ion implantation using the gate pattern as a mask, so an element with good matching between the seed and the gate can be formed. Therefore, the element formed by the manufacturing method of the present invention does not require the alignment margin between the seed and the gate compared to the conventional element formation process, and thus the area of the element can be reduced by the alignment margin. In addition, regarding the electrical characteristics, since there is no misalignment between the seed and the gate, the stray capacitance occurring at the junction of the source and drain is reduced, and the operating speed is increased by about 3%. Furthermore, the variation in properties between samples was also reduced. However, in Example 1, although it was confirmed that the characteristics were improved, since etching was used for element isolation, the gate 5
is present on the active region of the device. This caused leakage current to occur between the source and drain in the low concentration region L (see FIG. 2) on the side surface where the active region was etched. <Example 2> A 20 nm underlying oxide film 16 for LOGO8 oxidation and a 350 nm CVD nitride film are deposited on a p-type (100) single crystal silicon substrate 1, and then a nitride film pattern is formed in the element formation area by normal photoetching. 17 was formed, and using this nitride film pattern 17 as a mask, an oxide film 18 with a thickness of 800 nm was formed by normal wet oxidation (see Fig. 1C).
reference). Thereafter, the nitride film pattern 17 and the underlying oxide film 16 were removed, and a new 20 nm thick gate oxide film 19 was formed. After this, phosphorus (P) was implanted at 10 '' / (M 3
A gate 5 was formed by depositing a polycrystalline silicon film doped to a certain extent, and using the resist pattern 6 as a mask, dry etching was performed using SF diluted with hydrogen and gas to remove unnecessary portions of the polycrystalline silicon. Furthermore, oxygen ions 7 are implanted (160", 150KeV, 2X10") while leaving the resist pattern 6 used for processing the gate 5.
am-") to form an oxide film 8 directly under the regions that will become the source and drain (see Figure 3). Next, after removing the resist pattern 6 in oxygen plasma, As ions 9 are implanted. (60KeV, 5X
10"cm-") to form the source 10 and drain 11.
(See FIG. 3C) After that, a P-doped CVD oxide film (PSG) 13 was deposited as an interlayer insulating film, and a contact hole 14 was formed using a normal photoetching process. Finally, A1 is deposited and A1 is etched by a photo-etching process.
The S/D-8OIMOS transistor formed according to the above embodiment has a wiring 15 (see FIG. 1C).
Leakage current, which was a problem in Example 1, was not detected. In addition, the characteristics of the device in which the Ma film is formed directly under the source and drain by ion implantation are that the operating speed and soft errors due to alpha rays are reduced compared to the characteristics of the conventional device structure in which the insulating film 8 is not formed. However, when the insulating film 8 formed in Example 2 was examined, it was found that oxygen was precipitated in the film and the insulating film was not of good quality. <Example 3> After forming up to the gate oxide film 19 according to the process of Example 2, phosphorus (P) for the gate was first implanted without B1 ion implantation for Vth control.
Polycrystalline silicon lI4 doped to a certain extent was deposited. The thickness of this polycrystalline silicon film 4 was set to about 900 nm to be used as a mask during oxygen ion implantation later.
(see figure a). This polycrystalline silicon film 4 was formed into a polycrystalline silicon gate 5 by dry etching using SF gas diluted with hydrogen using the resist pattern 6 as a mask. After that, oxygen ion implantation 7 ("O" 150
An oxide film 8 was formed directly under the regions to be the source and drain (see FIG. 4). Since this oxide film 8 has oxygen precipitated in it, this sample is heat-treated in a nitrogen atmosphere (
1150°C for 2 hours). Next, the polycrystalline silicon film 5' on the oxide film 20 is removed by dry etching using hydrogen-diluted SF gas.
Furthermore, the oxide film layer 20 (thickness: approximately 0.4 μm) within the gate formed by oxygen ion implantation was removed using a hydrofluoric acid aqueous solution (see FIG. 4d). Here, by using dry etching conditions such that the etching rate of the polycrystalline silicon film 5' is 10 times or more the etching rate of the oxide film 19, regions that will later become the source and drain were secured. Next, after forming a 20 nm oxide film 21 by a normal oxidation process, B0 ions 3 for Vth control are implanted (1
80KeV, 1.4×10"am-"). For this B ion implantation, conditions were selected so that the surface of the substrate 1 directly under the gate 5 had the highest impurity concentration. Furthermore, As ion implantation was performed to form a source 10 and a drain 11 (see FIG. 4d), and the subsequent steps were performed in the same manner as in Example 2 (see FIG. 4e). No oxygen precipitation was detected in the oxide film 8 of the device formed by the above manufacturing process, and it was confirmed that the electrical characteristics were sufficiently improved. S/D-3° MOS formed by the above manufacturing process
FIG. 5 shows the results of comparing the electron mobility of the transistor with elements formed by other manufacturing processes. From the same figure, the electron mobility of device A without 1'O'' ion implantation was 600aa2/Vs, and the electron mobility of conventional S/D-5OI MOS transistor B was as high as about 750a++''/Vs. However, the variation was as large as ±8Qtyi2/Vs.
In the device C using the manufacturing method of the present invention, the electron mobility was approximately 840c++''/Vs, and the variation was small. Although the manufacturing method of a MOS transistor has been described, the manufacturing method of the present invention can also be applied to a manufacturing method of a p-channel device. S/D-8○I MO using self-alignment method to form insulating film layer
Since an S transistor is formed, the following effects can be obtained. 1. The conventional photoetching process for seed formation can be omitted. 2. Since the SOI layer is formed by implanting oxygen ions into the substrate, an SOI layer with the best crystallinity among the seeded SO imaging methods can be obtained. 3. It is possible to form finer elements than with conventional element manufacturing methods.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of Example 1 of the present invention, FIG. 2 is an external view of the main part of the element formed according to Example 1, and FIGS. FIG. 5 is a cross-sectional view showing the manufacturing process of Example 3, and a graph showing a comparison of electron mobilities of elements manufactured in different manufacturing processes. Explanation of symbols 1...Single crystal silicon substrate, 2...Oxide film, 3...
・V th control ion, 4... P-doped polycrystalline silicon film, 5... gate 6... photoresist pattern, 7... oxygen ion, 8... M edge film, 9...
Impurity ions, 10... Source, 11... Drain, 12... Resist pattern, 13... PSG film,
14... Contact hole, 15... A11Ii! Line film, 16... Base oxide film, 17... Nitride film, 18...
・Oxide film, 19...Gate oxide film, 20°21...
Oxide film reed drawing 圓り圓σ; Main issue! January poem Bokuru Ii Niji Kenri Teichii 乍e vertical β/ρ
-JolA Kyu S Tora〉Sununu

Claims (1)

[Claims] 1. A process of forming a gate using a normal gate process on a gate oxide film formed on the semiconductor surface, a process of forming an oxide film directly under the source/drain by implanting oxygen ions using the gate as a mask, and a process of forming an oxide film directly under the source/drain. 1. A method of manufacturing a semiconductor device, comprising a step of forming a source/drain by implanting impurities.