JPH02250512A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To increase an in-phase input range by securing the normal working of a transistor and preventing the generation of the large input offset voltage despite the increase of the in-phase input signal voltage. CONSTITUTION:When one of pairs of transistors TR 12/15 and TR 16/62 becomes inconductive, the current of an amplifying element TR 60 of a driving step changes. At the same time, the currents of active load TR 4, 7 and 11 also change. As a result, the overall balance is maintained and the offset voltage is never produced. Thus an in-phase input range is increased for a differential input amplifier circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a differential amplifier circuit, and particularly relates to a differential amplifier circuit with an expanded common-mode input range.

[Conventional technology]

Conventionally, differential amplifier circuits have been constructed of circuits as shown in FIG. 4 or 5. In Figure 4, N channel M
The OS transistors 27, 28, P-channel MO8 transistors 29 and 30 constitute an input differential amplification stage, and the P-channel MO8 transistors 31, N-channel MO8 transistors 26, and 7 transistors constitute a second drive stage.

N-channel MOS transistors 25 and 24.

The gates of the transistors 26 and 26 are connected in common and connected to one electrode of the transistor 24, the constant current source 32 and the transistor 24 are connected in series, and the transistor 31 is interposed between the VDD power terminal 36 and the Vss power terminal 37. The gate of
A transistor 31 is connected to one electrode of the transistor 30.
is connected to the Vo output terminal 35, and the gates of the transistors 27 and 28 are connected to v1. vN input terminal 3
3.34, and one electrode and gate of the transistor 29 are connected. v! , VN input terminal 33.34
The output voltage ■o varies depending on the differential input signal voltage (VN-vy) applied to the output voltage. However, when the common-mode input voltage ((Vs+Vx)/2) is 1< and takes a potential close to the voltage Vss of the power supply terminal 37, the drain current of the MOS transistor is (ID8=G(VO2-VT)", VO2>VTI. As can be seen from the expression, transistors 27.28
One or both transistors become non-conductive and no longer function as a differential amplifier.

FIG. 5 is a circuit diagram showing another conventional differential amplifier. i
In FIG. 15, the present circuit is obtained by configuring the MOS transistors in FIG. 4 with those of opposite channels. P channel MOS transistors 41, 42, N channel MO
S transistors 43 and 44 constitute an input differential amplifier, P channel MO8) transistor 40 and N channel MO
The S transistor 45 constitutes a second drive stage. Here, the common mode input voltage ((VN +V r )/23 bst
When the voltage at the l source terminal 36 (D) reaches a value close to VDD, one or both of the transistors 41 and 42 similarly ceases to conduct, and ceases to function as a differential amplifier.

There is a circuit shown in FIG. 3 as a circuit that avoids these phenomena. In FIG. 3, the circuit of FIG. 4 (a pair of P-channel MOS transistors 46 and 47, a pair of N-channel MOS transistors
S transistors 17 and 18, a pair of N channel MOS transistors 19 and 20, and a pair of P channel MO transistors 50 and 51 are added. transistor 2
The gate of 2, along with the gate of transistor 50, is %VI
The gate of the transistor 23 is connected to the input terminal 33, and the gate of the transistor 23 is connected to the vN input terminal 34 together with the gate of the transistor 51.
connected to the gates of transistors 17.18, connected to the series connection point of transistors 18.50, and connected to the gates of transistors 19.20 in common.
It is connected to the series connection point of transistors 51.19, one electrode of transistors 50.51 is connected in common, and connected to one electrode of transistor 47.
The other electrodes at 6°47 and the gates are commonly connected.

Here, the common mode input voltage is the voltage VS of the power supply terminals 36 and 37.
N-channel M of a differential pair even if it takes a value close to S or VDD
At least one of OS) transistors 22 and 23 or P-channel MOS transistors 50 and 51 is conductive and functions as a differential amplifier.

However, the circuit shown in Figure M3 has the following drawbacks. That is, since the N-channel MOS transistor 21 is a constant current source, when the transistors 22, 23 and 50.51 are all conductive, if the overall balance is maintained, the transistors 22.2
3. Or, when one of the pair of transistors 50, 51 ceases to conduct, an input offset voltage occurs. This input offset voltage is one of the important parameters representing the NI width accuracy of the differential amplifier, and is undesirable.

[Line layer that the invention seeks to solve]

The above-mentioned conventional differential amplifier circuit has the disadvantage that, as described above, when the common-mode input voltage approaches the power supply voltage vDD or VB2, it stops operating or the input offset voltage becomes large.

An object of the present invention is to solve the above-mentioned problems, and to enable the transistor to operate normally even when the common-mode input signal voltage becomes large.
An object of the present invention is to provide a differential amplifier circuit that prevents the occurrence of large input offset voltages.

[Means to solve the problem]

The configuration of the differential amplifier circuit of the present invention includes a 10th differential pair consisting of an N-channel MOS transistor and a P-channel MO8) transistor.
an input circuit consisting of a 20th differential pair made of transistors; a first current supply device that supplies a current proportional to the current flowing through the 10th differential pair; a second current supply device through which current flows;
A differential amplifier circuit comprising: a current supply device; and a drive stage having an active load having a current value equal to the sum of the current values of the second current supply device.

〔Example〕

FIG. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention. In FIG. 1, the differential amplifier circuit of this embodiment has a third
The circuit board includes a pair of N-channel MOS transistors 13.
．． 14, a pair of N-channel MOS transistors 4, 7,
A pair of P-channel MOS transistors 58 and 59, an N-channel MO transistor 8), and an N-channel MOS transistor 10 are added. Other parts are the same as in FIG. 3.

Here, the input part is differential N-channel MO8) transistors 12, 15, P-channel MO8) transistors 1.62
Consisting of The current of the 61°620 differential pair of transistors is
It is added to the signal passing through N-channel MOS transistor 12.15 via transistors 3.8 and 2.9 (N-channel MO8). The current flowing through the transistor 12.15 is the same as the current flowing through the N-channel MOS transistor 6.13°14.
, P-channel MO8) transistors 58, 59, and N-channel MO8) transistors 10, the active load N-channel MO8)? resistor 116ζ is connected. Transistors 13 and 14 include transistors 1 and 14.
A current proportional to 2.15 flows, and the common mode input voltage becomes voltage V
ss, and when transistor 12.15 becomes non-conductive, transistor 13.14 also becomes non-conductive at the same time.

The current flowing through the transistors 61 and 62 is detected by a current detection circuit made up of transistors 4 and 7. Transistor 4.7, together with transistor 11, is also an active load for the signal amplification element P-channel MO8) transistor R0.

In this embodiment, when one pair of transistors 12.15 or 61.62 becomes non-conductive, the current of the amplifier element transistor 60 of the drive stage changes; Since the current of both changes at the same time, the overall balance is maintained and no offset voltage occurs.

FIG. 2 is a circuit diagram showing a differential layer@circuit according to another embodiment of the present invention. In FIG. 2, the differential amplifier circuit of this embodiment does not include the transistor 4.7 in the circuit of FIG. ing.

In this embodiment, the current of the transistors 61, 62 is the same as that of the transistors 65, 63, 64, which constitute the current detection circuit.
) detected by transistor 10 and detected by transistor 12 .
13 is added to the active load transistor 1 for the amplification element transistor 60 in the drive stage.
A current value of 1 is determined. In this circuit as well, when one of the transistors 61 and 62 or the transistors 12 and 15 becomes non-conductive, the steady bias current of the transistor 60 decreases, but at the same time the current value of the transistor 11, which is the corresponding load, also decreases. As the voltage decreases, the overall balance is maintained and there is no offset voltage.

〔Effect of the invention〕

As described above, the present invention has the advantage of being able to configure a differential input amplifier circuit having a wide common-mode input range.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a differential amplifier circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a differential amplifier circuit according to another embodiment of the present invention, and FIGS. 5 are circuit diagrams showing conventional differential amplifier circuits. VDD...Positive power supply, Vss...Negative power supply, Vo...Output, V1*v,...
- Input, 32... Constant current source, 1 to 23, 24.
25.26.27.28.43. 44.45.66...N channel MOS transistors, 29 to 31.38 to 40.46 to 52.
53 to 62...P channel MO8) transistor, 36.37...Power terminal, 35...
・Output terminal. Agent Patent Attorney Susumu Uchihara DD VSS Figure

Claims (1)

[Claims] an input circuit consisting of a first differential pair consisting of N-channel MOS transistors and a second differential pair consisting of P-channel MOS transistors; a current supply device, a second current supply device that flows a current proportional to the current flowing through the second differential pair, and a current value of the first current supply device and the second current supply device. 1. A differential amplifier circuit comprising: a drive stage having an active load having a sum as a current value.