JPH0225069A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process by a method wherein gate electrodes of a memory cell of a double gate structure and a MOS transistor of a single layer gate structure are formed through a single photoengraving without making the surface of semiconductor substrate etched. CONSTITUTION:An Si substrate 11 is isolated to be insulated, and a SiO2 film 12, a gate electrode layer 13 of poly-Si, and a SiO2 film 14 are overlapped. A resist mask 15 is provided, and an opening is selectively provided to the SiO2 film 14. A second poly-Si gate electrode layer 16 and a high melting point silicide layer 17 are laminated. The gate electrodes are patterned through a single photoengraving process and concurrently subjected to an etching in common. A memory cell side A and a transistor side B are subjected to an etching under the same condition, so that two devices are formed on the same substrate at the same time as initially required.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a nonvolatile semiconductor memory element having a double gate structure and a MOS type device having a single layer gate structure. The present invention relates to improvements in a semiconductor device in which a transistor element and a transistor element are formed on the same semiconductor substrate, and a method for manufacturing the same.

[Conventional technology]

A conventional semiconductor device of this type includes a nonvolatile semiconductor memory element having a double gate structure (hereinafter also referred to as a memory cell with a double gate structure or simply a memory cell) and a memory cell attached to this memory cell. M of single layer gate structure
FIG. 2 shows a schematic configuration of a semiconductor device in which an OS type transistor element (hereinafter also simply referred to as a MOS type transistor) is formed on the same semiconductor substrate.

FIG. 2(A) is a cross-sectional view schematically showing the general configuration of each main manufacturing process in a memory cell portion with a double gate structure according to this conventional method, and FIG. FIG. 3 is a cross-sectional view schematically showing a schematic configuration for each main manufacturing process in a MOS transistor section formed at the same time as a memory cell section with a heavy gate structure; are formed on the same semiconductor substrate at the same time, but in this article, for convenience of explanation and for clear distinction from the configuration of one embodiment of the present invention described later, each of these parts will be described separately. It is expressed separately.

That is, in the conventional configurations shown in FIGS. 2(A) and 2(B), reference numeral 1 is a silicon semiconductor substrate, 2 is a first gate oxide film, and 3 is a first gate oxide film made of a polycrystalline silicon film. The gate electrode, 4 is a second gate oxide film, 6 is a second gate electrode made of a polycrystalline silicon film, and 7 is a high melting point metal silicide layer.
They are sequentially formed on a silicon semiconductor substrate 1.

Next, the manufacturing process using this conventional method will be described.

First, a field oxide film (not shown) is formed on the field region of the silicon semiconductor substrate 1 by a selective oxidation method, and then as shown in FIG. 2 (B-1), ! Only the 1lO5 type transistor part side is covered with resist 5.
As shown in FIG. 2 (A-), a first gate oxide film 2 is formed by a thermal oxidation method only on the element formation region side, and this first gate oxide film 2 is coated with
A polycrystalline silicon film is deposited and grown thereon by chemical vapor deposition to form the first gate electrode 3, and as shown in FIG.
As shown in -2), the resist 5 is removed by appropriate means.

Next, as shown in FIG. 2 (8-2) and (B-3), the entire surface of the memory cell part side of the double gate structure and the MOS type transistor part side, that is, the memory cell part of the double gate structure. on the first gate electrode Mi3 on the side, and on the semiconductor substrate 1 on the MOS transistor part side,
At the same time, a second gate oxide film 4 is formed by a thermal oxidation method, and a polycrystalline silicon film is deposited and grown on this second gate oxide film 4 by a chemical vapor deposition method to form a second gate electrode 6.
Further, a high melting point silicide layer 7 for lowering the resistance is formed on the second gate electrode Vi 6.

Next, as shown in Figure 2 (A-3) and (B-4), the memory cell side and the MOS type transistor side of the double gate structure were simultaneously coated by a single photolithography process. , patterning is performed for each gate electrode, respectively, and on the memory cell side, the high melting point silicide layer 7. Second gate electrode6. Second gate oxide film 4. 1st
Gate electrode 3. and the first gate oxidation f4@2, and the high melting point silicide layer 7. Second gate electrode6. and the second gate oxide film 4 are sequentially etched and formed at the same time, and in this way, a memory cell having a double gate structure and a MOS type having a single layer gate structure can be formed as expected. A transistor can be formed on the same semiconductor substrate at the same time.

[Problem to be solved by the invention]

However, in a semiconductor device manufactured as described above, in which a memory cell having a double gate structure and a MOS transistor having a single layer gate structure are formed on the same semiconductor substrate. , the gate electrode on the MOS transistor part side in this S, that is, in this case, the second
The gate electrode is made of a low-resistance polycrystalline silicon film, and the etching process for patterning each gate electrode in the final process can be performed under different etching conditions through a single photolithography process. A high melting point silicide layer, a second gate electrode, a high melting point silicide layer, a second gate electrode,
Second gate oxide film.

First gate electrode and five layers of first gate oxide film, MO
Since the three layers of the high melting point silicide layer, the second gate electrode, and the second gate oxide film are applied simultaneously on the S-type transistor side, the amount of patterning required for each gate electrode is reduced. The MOS type transistor part side, which has a large number of layers, is etched to the surface of the silicon semiconductor substrate, which increases the number of crystal defects and distortions in the silicon semiconductor substrate. For example, problems such as an increase in junction leakage occur in the electrical characteristics of the diffusion layer and the like.

On the other hand, in order to avoid this, it is necessary to perform etching for patterning the gate electrodes of the memory cell part having a double gate structure and the MOS transistor part having a single layer gate structure under mutually different etching conditions. It is conceivable to perform molding for each part separately, but this would require the photolithography process to be performed at least twice, which would undesirably complicate the manufacturing process. there were.

This invention was made to solve these conventional problems, and its purpose is to combine a memory cell portion with a double gate structure and a MOS with a single layer gate structure.
Etching molding for patterning each gate electrode with a semiconductor transistor part can be performed by only one photolithography process, and the surface part of a semiconductor substrate is not etched by this process. . An object of the present invention is to provide a semiconductor device of this type and a method for manufacturing the same.

[Means to solve problems]

In order to achieve the above object, a semiconductor device and a method for manufacturing the same according to the present invention are provided as follows. For a memory cell portion having a double gate structure consisting of a second gate electrode,
Regarding the type transistor section, the first. A second gate electrode is simultaneously formed by the same means, and a second gate electrode is formed on the first gate electrode in this MOS type transistor section. The second gate electrodes are connected to each other.

That is, the present invention provides a semiconductor device in which a nonvolatile semiconductor memory element having a double gate structure and a MOS type transistor element having a single layer gate structure are formed on the same semiconductor substrate, wherein the nonvolatile semiconductor memory element Common to the part and the MOS transistor element part, a first gate oxide film, a first gate electrode, a second gate oxide film, and a second gate electrode are provided, respectively.

and high melting point silicide layers are sequentially formed,
The first part of the 105 type transistor element section. 2nd gate 'H
, and are connected to each other through a contact hole opened in a second gate oxide film.

The present invention also provides a method for manufacturing a semiconductor device in which a nonvolatile semiconductor memory element having a double gate structure and a MOS transistor element having a single layer gate structure are formed on the same semiconductor substrate, Semiconductor memory element section and M
A step of sequentially and commonly forming a first gate oxide film, a first gate electrode, and a second gate oxide film on the semiconductor substrate with the OS type transistor element part, and a step corresponding to the MOS type transistor element part. A step of opening a contact hole in the second gate oxide film, forming a second gate oxide film and a high melting point silicide layer in common on these, and passing the second gate oxide film through the contact hole.
connecting the gate oxide film to the first gate oxide film;
The high melting point silicide layer, the second gate electrode, the second gate oxide film, and the first gate electrode are formed by photoengraving the nonvolatile semiconductor memory element portion and the MOS transistor element portion.

and a step of simultaneously etching the first gate oxide film.

(Function) Therefore, in the present invention, the first and second gate electrodes are simultaneously formed in the nonvolatile semiconductor memory element portion and the MOS transistor element portion by the same means, and the first and second gate electrodes are simultaneously formed in the nonvolatile semiconductor memory element portion and the MOS transistor element portion. 1° Since the second gate electrodes are connected to each other, the first. The etching conditions for patterning on the second gate electrode are matched, and this etching formation can be performed in just one photolithography process, making it possible to simplify the manufacturing process. During this molding,
There is no danger that the surface of the semiconductor substrate will be etched.

〔Example〕

Hereinafter, one embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to FIG.

FIG. 1(^) is a cross-sectional view schematically showing the general configuration of each main manufacturing process in a memory cell portion with a double gate structure to which this embodiment method is applied, and FIG. )
2A and 2B are cross-sectional views schematically showing the general configuration of each main manufacturing process in a MOS transistor part with a single-layer gate structure that is attached to the memory cell part with a double-gate structure and formed simultaneously with the above-mentioned memory cell part with a double-gate structure. In this case, the memory cell section and the MOS transistor section are both on the same semiconductor substrate and formed at the same time using the same procedure, but based on the reasons mentioned above, these sections are are shown separately.

That is, in these FIGS. 1(8) and (B), the method of this embodiment first involves the steps shown in FIG. 1(A-1),
As shown in (B-1), after forming a field oxide film (not shown) in the field region of the silicon semiconductor substrate 11 by selective oxidation method, the memory cell part side of the double gate structure corresponding to the element formation region is A first gate oxide film 12 is commonly formed on the entire surface of the MOS transistor section side using a thermal oxidation method, and a polycrystalline silicon film is formed on this first gate oxide film 12 using a chemical vapor deposition method. A first gate electrode I3 is similarly commonly formed by depositing and growing, and a second gate oxide film I4 is similarly commonly formed on this first gate electrode I3 by a thermal oxidation method. .

Next, as shown in FIGS. 1A-2 and 1B-2, the entire surface of the memory cell side and the MOS transistor side of the double gate structure is covered with a resist 15, and this resist 15 is After opening the portion corresponding to the second gate electrode on the MOS transistor portion side, the second gate oxide film 14 is selectively etched until it reaches the second gate electrode 13, thereby opening a contact hole 13a.

Thereafter, as shown in FIGS. 1A-3 and 1B-3, after removing the resist 15 of the second gate oxidation [14-1], chemical A second polycrystalline silicon film is deposited and grown using a vapor phase epitaxy method.
The gate electrode 16 is formed in common, but at this time, MO
On the S-type transistor side, the contact hole 13
Through a, these first. Second gate electrode 14.16
are electrically connected to each other, and furthermore, a high melting point silicide layer I7 is formed on the second gate electrode 16 to lower the resistance.

Next, as shown in FIGS. 2(A-4) and (B-4), the memory cell side and the MOS transistor side of the double gate structure were simultaneously coated by a single photolithography process. , respectively, and patterned the high melting point silicide layer 17. on both the memory cell side and the +lIO3 type transistor side.
Second gate electrode 16. Second gate oxide film 14. First gate electrode 13. and in the order of the first gate i/oxide film 12,
They are commonly etched and formed at the same time.

At this time, these memory cell side and MO
On the S-type transistor side, since the etching conditions are mutually matched, the MOS is not etched as in the conventional method.
In this way, the surface of the silicon semiconductor substrate is not etched on the type transistor side, and the memory cell having a double gate structure is formed as expected.
A MOS transistor with a single-layer gate structure can be formed simultaneously on the same semiconductor substrate.

〔Effect of the invention〕

As detailed above, according to the present invention, in a semiconductor device in which a nonvolatile semiconductor memory element having a double gate structure and a MOS type transistor element having a single layer gate structure are simultaneously formed on the same semiconductor substrate, Common to the nonvolatile semiconductor memory element section and the MOS transistor element section,
A first gate oxide film, a first gate electrode, a second gate oxide film, a second gate electrode, and a high melting point silicide layer are sequentially formed on each of the first gate oxide film, first gate electrode, second gate oxide film, second gate electrode, and high melting point silicide layer. Since the second gate electrodes are connected through the contact hole opened in the second gate oxide film, the etching conditions for the nonvolatile semiconductor memory element part and the MOS transistor element part are matched, and each of these parts is No. 1 in The etching process for patterning the second gate electrode can be carried out in just one photolithography process, simplifying the manufacturing process. There is no risk of crystal defects in the substrate.

It has excellent features such as being able to reduce distortion and normalizing and improving the electrical characteristics of the diffusion layer and the like.

[Brief explanation of the drawing]

FIG. 1(A) is a cross-sectional view schematically showing the general configuration of each main manufacturing process in a memory cell portion with a double gate structure to which an embodiment of the method for manufacturing a semiconductor device according to the present invention is applied. , FIG. 2(B) is a cross-sectional view schematically showing the general configuration of each main manufacturing process in the MOS transistor section formed simultaneously with the memory cell section of the double gate structure, and FIG. (A) is a cross-sectional view schematically showing the general configuration of each main manufacturing process in a memory cell portion with a double gate structure in a conventional semiconductor device manufacturing method, and (B) is a cross-sectional view of the same double gate structure in a conventional method for manufacturing a semiconductor device. FIG. 3 is a cross-sectional view schematically showing a schematic configuration for each main manufacturing process in a MOS transistor section formed simultaneously with a memory cell section of a gate structure. 11... Silicon semiconductor substrate, 12... First gate oxide film, I3... First gate electrode, 14...
・Second gate oxide film, 15...Resist, 16...
...Second gate electrode, 17...High melting point silicide layer. Figure 2 (A) (B)

Claims (2)

[Claims] (1) A nonvolatile semiconductor memory element with a double gate structure and a MOS transistor element with a single layer gate structure,
In a semiconductor device formed on the same semiconductor substrate, the nonvolatile semiconductor memory element portion and the MOS transistor element portion each include a first gate oxide film, a first gate electrode, and a second gate oxide film. , a second gate electrode, and a high melting point silicide layer, and the MOS
1. A semiconductor device characterized in that first and second gate electrodes of a type transistor element portion are connected through a contact hole opened in a second gate oxide film. (2) A nonvolatile semiconductor memory element having a double gate structure and a MOS transistor element having a single layer gate structure,
A method of manufacturing a semiconductor device formed on the same semiconductor substrate, wherein a first gate oxide film,
a step of sequentially commonly forming a first gate electrode and a second gate oxide film; a step of opening a contact hole in the second gate oxide film corresponding to the MOS transistor element portion; forming a second gate oxide film and a high melting point silicide layer in common, and connecting the second gate oxide film to the first gate oxide film through the contact hole; The high melting point silicide layer, the second gate electrode, the second gate oxide film, the first gate electrode, and the first
1. A method of manufacturing a semiconductor device, comprising at least the step of simultaneously etching gate oxide films.