JPH02252186A - First-in first-out memory - Google Patents

Abstract

PURPOSE:To reduce the number of memories by incorporating a timing control part to deviate timing and to input data to a memory array or to output the data in a first-in first-out (FIFO) memory. CONSTITUTION:When writing operation is executed, data Din 0 - Din 7 to be written appear on a data bus. However, at such a time, a write clock 7 is always inputted to a timing control part 1 in advance and the data Din 0 - Din 7 are taken into an input data latch part 4 according to a control signal 5 from the control part 1. Simultaneously, a write address control part 2 is operated by the control signal 5 and a generated address signal 6 is inputted to an address decoder 3. Then, a position, where the data are written, on a memory cell 9 is calculated by a decoder 3 and writing is executed. When reading operation is executed, samely, a control signal 16 is generated from the control part 1, to which a read clock 8 is inputted, and inputted to an address control part 10 and the data are read from the memory 9 by using an address signal from this part 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a first-in, first-out memory, and particularly to a technique suitable for a data communication device having a plurality of different bus widths.

[Conventional technology]

For example, Nikkei Electronics 1,987゜5.18 describes first-in first-out memory.
No. [1M chip dedicated to field memory.

There is a technology described in ``Let's get everything together for VTR/TV all at once''.

This technology is a data buffer, which is used to temporarily store data between buses and blocks with different operating speeds, and the number of data input bits and the number of data output bits are the same, 4 bits each.

[Problem to be solved by the invention]

For example, when multiple CPUs are configured such that one has a 16-bit bus and the other has an 8-bit bus, when attempting to transfer data from the 16-bit side to the 8-bit side between these buses, the above-mentioned conventional technology Both the number of input bits and the number of data output bits are 4 bits, and the input target is 16 bits wide, so 4 memories are required, and when outputting to the 8-bit side, 2 memories each (4 bits x 2
(8 bits) It is necessary to alternately shift the timing and input the read clock to the first-in, first-out memory, and it is necessary to externally attach flip-flops, selectors, etc.

Similarly, when the output bus width is larger than the input bus width, write clock control is required.

An object of the present invention is to eliminate the need for external read/write clock control across multiple first-in, first-out memories;
The goal is to reduce the amount of memory.

[Means to solve the problem]

The above purpose is to change the number of data inputs and the number of data outputs by incorporating a timing control unit in the first-in-first-out memory to alternately shift the timing and manually input data to the memory array or output data from the memory array. This can be achieved by using a memory with 16 inputs and 8 outputs, or 8 inputs and 4 outputs.

In the above example, when transferring from a 16-bit bus to an 8-bit bus,
If the number of inputs is 16 and the number of outputs is 8, only one first-in, first-out memory is required and there is no need to control read clocks across multiple memory. Also, if the number of inputs is 8 and the number of outputs is 4, two first-in, first-out memories are required, but since the readout timings of the two are the same, the same readout clock is just given, and there is no need to shift the timing.

[Effect]

In other words, in the case of m inputs and m outputs (m, -n are integers greater than or equal to 1, m〆L), m bits of data are written to the memory cell array by the write clock, and in the case of reading, generally at the write frequency. m bits are output by a read clock with a frequency m/71 times higher.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the main parts of a first-in, first-out memory according to the present invention. In this example, 8 input data, (bit)
, take up a memory with four output data (bits).

In FIG. 1, ■ is a timing control section that controls the timing for generating an address in the write address control section 2 using a control signal 5 based on the write clock 7, and the input data DinO for the manual data latch section 4.
-Notify the timing to import Din7. Similarly, based on the read clock 8, a control signal 14 notifies the read address control unit 10 of the timing to generate an address and the output data latch unit 1:3 of the timing to take in the output data DoutO to Dout3.

2 is a write address control section, which generates an address 6 to be written according to a control signal 5 from the timing control section 1, and a write address decoder 3.
send to 3 is a write address decoder which decodes the address signal 6, determines the position to which the data taken into the input data latch unit 4 should be written, and writes the data to a predetermined position. Reference numeral 4 denotes an input data latch section which takes in 8-bit input data Dine-Din7 based on a control signal 5 generated from the timing control section 1.

Reference numeral 5 denotes a control signal, which is generated by the timing control section 1 and informs the write address control section 2 of the timing to generate an address and the input data latch section 4 of the timing of fetching data. Reference numeral 6 denotes an address signal, which is generated by the write address control unit 2 and indicates an address to which data is to be written.

7 is a write clock, and the writing speed is determined by the frequency (cycle) of this clock.

8 is a read clock, and the read speed is determined by the frequency (cycle) of this clock. In this example, the input is 8 bits and the output is 4 bits, so the frequency of the read clock 8 is usually twice that of the write clock 7 (=8/4
).

Reference numeral 9 denotes a memory cell, and in this example, since the number of output pins is 1 to 4, the memory cell is handled in units of 4 bit columns. In other words, when writing data, the upper 4 bits DinO=D
in3 is on the memory cell 9-1 side (left side cell), and lower 4 bits Din4 to Din7 are on the memory cell 9-2 side (left side cell).
right cell) in the specified row. When reading, data is read alternately from either the memory cell 9-1 side or the memory cell 9-2 side.

Reference numeral 10 denotes a read address control section, which generates an address 15 to be read based on a control signal 14 from the timing control section 1 and sends it to the read address decoder 11. In addition, the above-mentioned memory cell 9-1 or 9-
A signal 16 is sent to a read data selector 12 which selects the data read from the second side.

Reference numeral 11 denotes a read address decoder which decodes the address signal 15 to determine the row to be read and reads it from a predetermined position. 12 is a read data selector;
Based on the control signal 16, 4 bits of data from either one of the memory cells 9-1 and 9-2 are taken out and sent to the output data latch section 13. Reference numeral 13 denotes an output data latch section, which takes in data DoutO to Dout3 sent from the read data selector 12 based on a control signal 14 generated by the timing control section 1. Reference numeral 14 denotes a control signal, which is generated by the timing control section 1 and informs the read address control section 10 of the timing to generate an address and the timing of fetching the output data to the output data latch section. 15 is an address signal 61 generated by the read address control section 10 and indicating the address from which data should be read.
Reference numeral 6 denotes a read data selection control signal, which is input to the read data selector 12 and indicates which side of the 9-1 and 9-2 memory cells is to be extracted.

FIG. 2 shows an example in which the memory shown in FIG. 1 is used across buses with different bus widths, and data is input from the 16-bit bus side and output to the 8-bit bus side.

17 and 18 are the first-in first-out memories shown in FIG.
15 to upper side DinO”Din7 and lower side Din8~D
In15 is divided into 8 bits and input to each memory, and a total of 4 bits from each memory is output to the 8-bit bus 20.

19 is a 16-bit bus on the input side, and 20 is an 8-bit bus on the output side.

7 is a write clock, and 8 is a read clock. The frequency of the read clock 7 is twice that of the write clock 8, and is input to the first-out look-ahead memories 17 and 18 at the same timing.

Next, the operation of this embodiment will be explained with reference to FIG. The write operation and the read operation will be explained in this order.

In the case of a write operation, first, data D in O to Din7 to be written to the memory is placed on the data bus. The write clock 7 is constantly input to the timing control section 1, and the write clock 7 is inputted to the timing control section 1 at all times.
7 is a cycle in which data is input to the input data latch unit 4 by the control signal 5 from the timing control unit 1.
be taken in.

At the same time, the address signal 6 of the memory cell to which the data fetched by the write address is to be written is sent by the control signal 5.
occurs. Since this first-out first-read memory is serial input/output, the generated address is the next line of the address line written in the previous write cycle (in this example, one line means an 8-bit sequence). show. The address signal 6 generated by the write address control unit 2 enters the write address decoder 3. The write address decoder 3 determines the position to write on the memory cell 9, and the value is set to the nth row (n is an integer greater than or equal to 0). ), the upper 4 bits of input data, DinO to Din3, are
In the second row of memory cell 9-1 (left side), lower 4 bits D
in4 to Din7 are the n-th memory cell 9-2 (right side)
written to the line. The above is the write operation.

In the case of a read operation, the read clock 8 is always input to the timing control section 1, but when focusing on one particular cycle, the timing control section 1 generates a control signal 16 according to that cycle. This signal is input to the read address control section 10,
In the read address control unit 10, the memory cell 9
An address signal 15 for data to be read is generated.

Since the data to be read is 4 bits, this address signal is the row number of the memory cell and 9-1 (right side) 9-2 (
It also includes information on which side (on the left) is to be read. Furthermore, since this memory is a serial input/output type, the generated address is a position obtained by adding 4 bits from the address read in the previous read cycle. The address signal 15 generated from the read address controller 1 to the roll unit 10 enters the read address decoder 11.
Then, the position on the memory cell 9 to be read is determined, 4 bits are read from the memory cell 9-1 or 9-2, and the read data is output to the read data selector 12.

The read data selector 12 receives the 4-bit data output from the memory cell 9-1 or 9-2 based on the read data selection control signal 16 output from the read address control unit 10, and the data latch unit 13 receives the 4-bit data output from the memory cell 9-1 or 9-2.
Control signal 1 output from timing control section 1
4 takes in the 4 bits of data sent from the read data selector 12 and sends it to the outside as DoutO-Do.
Output as ut3. The above is the read operation.

Next, the operation shown in FIG. 2 will be explained. When used across buses, it is used as a buffer to temporarily store data and adjust time between buses with different operating speeds.

In this example, transfer to a 16-bit bus or a 68-bit bus is considered.

Input data of 16-bit bus 19 D in O to D i
, n 15 are taken into the first-in, first-out memory 17.18 by the write clock 71 and written serially. The upper 8 bits DinO to Din7 are taken into the memory 17, and the lower 8 bits Di, n8 to Din15 are taken into the memory 18.

On the other hand, in the case of reading, four bits are serially read out from each memory 17, 18 from a predetermined position by the read clock 8. The 4 bits of data read from the memory 17 are DoutO to Dout3, and the 4 bits of data read from the memory 18 are Dout4-Dout3.
The signals are collected as Dout7 and output to the 8-bit bus side.

Even when there are multiple memories (two or more) like this, the read/write) clocks can be input at the same timing without phase shift to all memories. When using the first-in first-out memory of a book, on the output side of this example, the first memory and the second [1
It is necessary to input the read clock of the memory with a half phase shift, which requires extra circuitry and control.

The first-in, first-out memory mentioned as an example has eight input data and four output data, so two are required for transfer between a 16-bit 1-bus and an 8-bit bus, but the number of input and output of the first-in first-out memory is limited between transfer buses. If it is the same as Bitsuke, you only need one. (In this example, it is a first-in, first-out memory with 16 pieces of input data and 8 pieces of output data.) Also, in this example, the case where the input bus width is larger than the output bus width has been explained, but the output bus width is larger than the input bus width. If the size is larger, the read selector 12 in FIG. 1 replaces the write data selector, writes to the memory array alternately on the left and right of the row, reads only one row, and other input/output The same explanation can be given by replacing it.

〔Effect of the invention〕

As explained above, according to the present invention, when using first-in, first-out memories for bus crossing between different bus widths, the number of first-in, first-out memories is smaller than before, and the write or read clock timing due to the use of multiple memories is the same on the bus width side. This has the effect of making clock control easier because input can be made at the right timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a first-in, first-out memory according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of how the memory shown in FIG. 1 is used. 1...Timing control, 2...Write address control, 7...Write clock, 8...
Read clock, 9...Memory cell, 10...Read address control, 12...Read selector.

Claims (1)

[Claims] 1. A mechanism that latches input data signals using a write clock, a write address control mechanism that controls the data to be stored in the order in which the data is received, a memory cell that temporarily stores data, and a memory cell that uses a read clock. It has a read address control mechanism that controls sequential reading of data from memory cells, a mechanism that latches and outputs read data, and a read or write data selector, and changes the number of data read or written to memory cells. A first-in, first-out memory characterized in that the number of data inputs and the number of data outputs are different.