JPH022521A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To suppress the generation of a defect due to the operation defect of a thin film transistor(TFT) by arranging at least two TFTs in the vicinity of respective picture element electrodes and connecting at least two TFTs between picture element electrodes or their signal lines in parallel. CONSTITUTION:Two thin film transistors TFT2 and TFT3 are arranged adjacently to one side of a rectangular picture electrode 1 which has a notch at one corner part. The TFTs 2 and 3 are connected to the picture electrode 1 by drain electrodes 4 and 5. Then the source electrodes 6 and 7 of the TFTs 2 and 3 are connected to a source bus line 8. Thus, the TFTs 2 and 3 are connected between the picture element electrode 1 and source bus line 8 in parallel. Then the interval between the TFTs 2 and 3 is made as large as possible so as to reduce the danger of the occurrence of an operation defect to both the TFTs 2 and 3 due to the wire breaking of the source electrodes 6 and 7 and drain electrodes 4 and 5. Therefore, when at least one of the two TFT operates normally, a signal is correctly supplied to the picture element electrode. Consequently, the generation of the defect due to the operation defect of the TFT is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix substrate for constructing an active matrix type display device in combination with a liquid crystal or the like.

(Prior Art) In recent years, thin film transistors have been used in panel display devices such as liquid crystal display devices.
Active matrix substrates using tor (hereinafter abbreviated as TPT) as picture element driving elements are widely used. In such an active matrix substrate.

As shown in FIGS. 20 to 22, an insulating glass substrate 2
A large number of picture element electrodes 200 are arranged in a matrix on 10 . i to the signal written on each picture element electrode 200
n indicates that the picture element electrodes are arranged in m rows and n columns. A TFT 201 is provided adjacent to each picture element electrode 200, and a drain electrode 202 of the TPT 201 is connected to the picture element electrode 200. In order to supply signals to the picture element electrodes 200, a large number of scanning lines 205 are wired in parallel, and a large number of signal lines 2 intersect with the scanning lines 205.
06 are wired in parallel.

The gate electrode 203 and source electrode 204 of each TFT 201 are connected to the scanning line 205 and the signal line 206, respectively. The scanning line 205 and the signal line 206 are electrically insulated at each intersection. Below, scan line 20
5 and the signal line 206 are called a gate path line and a source path line, respectively.

The manufacturing process of the conventional active matrix substrate shown in FIGS. 21 and 22 will be explained. Insulating glass substrate 2
A gate pass line 205 made of tantalum (hereinafter referred to as Ta) is formed on 10. Next, silicon nitride (hereinafter referred to as SiN) is deposited.

A gate insulating film 211 is used. Intrinsic amorphous silicon (hereinafter referred to as a-3i(i)) is deposited on the gate insulating film 211 and patterned to form a semiconductor layer 212. SiN is deposited on the semiconductor layer 212.

The etching stopper layer 213 is formed by patterning. On top of this, + type amorphous silicon (hereinafter referred to as a
-3i (referred to as "n")) l'1214 is laminated and patterned.Next, titanium (referred to as Ti hereinafter) is deposited and patterned to form the source path line 206.
and a drain electrode 202 is formed. The end of the branch line of the source pass line 206 becomes the source electrode 204.

Finally, ITO (Indium-Tin-Oxide) is deposited and patterned to form the picture element electrode 200.

At the intersection of the gate pass line 205 and the source pass line 206, a +a-Si(i)/a-5i(n'') layer 215 and an etching stopper 1216 made of 5iNX are placed between the gate pass line 205 and the source pass line 206. Intervention is provided.

(Problems to be Solved by the Invention) In a display device using such an active matrix substrate, disconnection of the gate pass line 205 or source pass line 206 or line leakage between them,
Defects caused by malfunction of the TFT 201 become a problem. If the gate lot line 205 or the source pass line 206 is disconnected, a linear defect will occur, and the TPT2
A pixel defect occurs due to the malfunction of 01. Such defects significantly reduce the display quality of a display device.

Conventionally, countermeasures have been taken to address such problems in the manufacturing process, but it has been difficult to sufficiently suppress the occurrence of defects.

The present invention was made in view of the current situation,
The purpose is to provide an active matrix substrate that can sufficiently suppress the occurrence of defects due to malfunction of TPT in a display device using an active matrix substrate and has an excellent manufacturing yield.

(Means for Solving the Problems) An active matrix substrate of the present invention includes an insulating substrate,
An active matrix substrate comprising picture element electrodes arranged in a matrix on the insulating substrate and a plurality of signal lines arranged on the insulating substrate, the active matrix substrate having a plurality of signal lines arranged in the vicinity of each picture element electrode. (Both are equipped with two thin film transistors,
The at least two thin film transistors are connected in parallel between the picture element electrode and one of the signal lines, thereby achieving the above object.

Furthermore, the active matrix substrate of the present invention includes:

The gate insulating film of the thin film transistor may have at least two stacked layers, thereby achieving the above object.

(Example) The present invention will be described below with reference to Examples.

Fig. 1 shows the main part of an embodiment of the present invention, - Two TPTs 2.3 are arranged adjacent to the - sides of a roughly quadrilateral picture element electrode 1 (made of ITO) with notches at the corners. has been done. TPT
2.3 is connected to the picture element electrode 1 by a drain electrode 4.5. Also, the source electrode 6 of TPT2.3.
7 is connected to the source lot line 8. In this way, the TPT 2.3 is connected in parallel between the picture element electrode 1 and the source pass line 8.

Therefore, it is sufficient if at least one of TPT2.3 operates normally. TPT 2.3 is a TP extending from the gate lot line 9 in parallel to the source pass line 8.
It is formed on the read gate line 10 for T connection,
TPT2゜3 of lead gate line 10 for TPT connection
The part directly below is the gate electrode. Source electrode 6.
TPT2.3 due to disconnection of 7 or drain electrode 4.5, etc.
In order to reduce the risk of malfunction occurring in both
The interval between TPT2 and TPT3 is set as large as possible. Further, the gate insulating films of TPTs 2 and 3 have a two-layer structure in which a TazOs film and a 5iNX layer are laminated, as will be described later.

The source pass line 8 is attached to the gate lot line 9 made of Ta.
Bypass line 1 for 5 main lines 11 other than the intersection with
2 is provided. By providing the bypass line 12, the risk of Ta peeling off and disconnection is reduced. Further, by providing the bypass line 12, the effective line width of the gate pass line 9 is increased and the resistance is reduced. Gate pass line 9
In the hatched area, a Ti film, which is a source pass line material, is laminated on the Taz05 film and SiN layer layered on the 1-gate pass line 9 when forming the source pass line 8. It is wired. This Ti
The film is connected to a gate pass line 9 via a through hole 13 drilled in the TazOs film and the 5iNX layer. This double wiring effectively prevents disconnection of the gate pass line 9 and reduces resistance. As mentioned above, the bypass line 12 connects the gate pass line 9 and the source pass line 8.
It is not provided at intersections with This is to avoid an increase in the possibility of inter-line leakage between both pass lines and an increase in stray capacitance due to an increase in the number of crossings.

The source pass line 8 made of Ti includes a gate pass line 9.
A bypass line 14 is provided at the intersection. At the intersection where the source pass line 8 crosses over the gate pass line 9, there is a high risk that the Ti of the source pass line material will peel off and breakage will occur, but this risk is reduced by the bypass line 14. At the intersection, between the gate pass line 9 and the a-Si(i) layer,
Etching stopper layer 16 and a-5 made of SiN
A laminated structure of i(n'') layers 15 is independently interposed at each intersection.The source lotus line 8 and the gate pass line 9 are electrically insulated by these layers. In the hatched area, double wiring with Ta, which is the gate pass line material, is made for the purpose of preventing disconnection and reducing resistance.

In this part, a pattern of Ta, which is a gate lot line material, is formed when the gate pass line 9 is formed, a 5iNX layer is formed thereon, and a source pass line 8 is formed on the 5iNX layer. What is Ti in the source lotus line material and Ta in the gate lotus line material?

It is connected via a through hole 17 drilled in the 5iNX layer interposed between the two. Furthermore, ITO, which is a picture element electrode material, is deposited on the entire source pass line 8 and the double wiring portion of the gate pass line 9 for reinforcement.

In this way, in this embodiment, two TPTs 2.3 are provided for each picture element electrode 1.

Reliability is increased by providing redundancy to the gate lotus line 9 and the source lotus line 8.

Next, in order to understand the details of the structure of the active matrix substrate of this example, the manufacturing process of the substrate will be explained.

(1) As shown in Figure 8, a transparent insulating glass substrate 2
A Ta film 21 is vapor-deposited on the film to a thickness of 3,000.

(2) Process the Ta film 21 by photolithography.

As shown in FIGS. 2 and 9, the gate pass line 9.
Read gate line for TPT connection 10. and a double wiring portion 22 of the source path line. A part of the gate line 10 for TFT connection has two gate electrodes 23.
．． It is said to be 24.

(3) As shown in Figure 10, the gate pass line material T
The surface of a is oxidized by anodic oxidation to form a TazOs film 25 with a thickness of 5. However, since the double wiring portion 22 is separated from the gate pass line 9, it is not oxidized.

The thickness of the TazOs film 25 is 53,000.

(4) +5iNJ26. by plasma CVO method. a
-3i (i) layer 27. and 5iNX layer 28 are sequentially grown (FIG. 11).

The thickness of each layer is 3000, 300, and 1, respectively.
000 people. SiN, JE! 26 is TazO
Together with the s film 25, a gate insulating film having a film thickness of 5 PT is formed.

(5) As shown in FIGS. 3 and 12, the SiNx layer 28 is processed by photolithography to form an etching stopper layer 29 on the gate electrodes 23 and 24 and a source lot line and a gate pass line 9 to be formed later. An etching stopper layer 16 is formed at the intersection with the etching stopper layer 16.

(6) As shown in FIG. 13, the a-5i (n'') layer 30 is grown to a thickness of 1000 layers by plasma CVD.

(7) As shown in FIGS. 4 and 14, a-3i(n") layers 30 and a-3
t(i) N27 is processed to remove portions other than the portion 31 above the gate electrode 23 and 24 and the intersection portion 15 between the gate pass line 9 and the source pass line.

(8) As shown in FIGS. 5 and 15, through holes 13 and 17 are formed in the 5iNX layer 26 and the TazOs film 25 in order to connect the upper and lower wiring when double wiring is performed. . Two through holes 13 and 17 are formed at each location in case of opening defects in the photolithography process.

(9) Ti, which is a source pass line material, is deposited by sputtering to form a Ti film 32 (FIG. 16). The Ti film 32 is connected to Ta through the through hole 13.17.
connected to the membrane of

0ω As shown in FIGS. 6 and 17, the Ti film 32 is processed by photolithography to form the source lot line 8.
．． Source electrodes 6 , 7 . connected to source lot line 8 .
A double wiring portion 33 of the drain electrodes 4 and 5 and the gate pass line 9 is formed. At this time.

a-Si (n”) under the Ti film 32 in the TPT portion
) layer 31 is also processed by etching and is divided into a source electrode side and a drain electrode side. This etching is stopped at the etching stopper layer 29.

(11) As shown in FIG. 18, I
TO is deposited on the entire surface by sputtering, and the film thickness is l.
000 ITO film 34 is formed.

02) As shown in FIGS. 7 and 19, the ITO film 34 is patterned by photolithography to form the picture element electrode 1. i to reinforce the pattern of Ti
TO+ pattern 34 is also applied to areas other than picture element electrode 1.

It is processed into the same pattern as the Ti pattern (see FIG. 6).

(Effects of the Invention) In the active matrix substrate of the present invention, two TPs are connected in parallel between each picture element electrode and the signal line.
Since TPT is provided, if at least one of the two TPTs operates normally, a signal is correctly supplied to the picture element electrode. Therefore, it is possible to sufficiently suppress the occurrence of defects caused by malfunction of the TPT in a display device such as a liquid crystal display device using the active matrix substrate of the present invention.

Such an active matrix substrate has an excellent manufacturing yield, and also brings about a significant improvement in the manufacturing yield of display devices using the active matrix substrate.

Furthermore, by forming the gate insulating film of the TPT into a two-layer structure, the possibility of a short circuit between the gate and the source and between the gate and the drain of the TPT can be made very small. Therefore, an active matrix substrate with extremely high reliability of TFTs (l!iI) can be realized.

Figure 1 is a plan view of the main part of an embodiment of the active matrix substrate of the present invention, and Figures 2 to 7 are plan views of the main part showing the manufacturing process of the embodiment. 8 to 19 are cross-sectional views taken along line A-A in FIG. 1 at each stage of the manufacturing process, of which FIG. 9 is a cross-sectional view of FIG.

12, 14, 15, 17, and 19 are lines BE in FIG. 2 and lines CG in FIG. 3, respectively.

D-D line in Figure 4, E-E line in Figure 5, F-F in Figure 6
20 is a schematic plan view of an example of a conventional active matrix substrate;
FIG. 21 is a plan view of a main part of an example of a conventional active matrix substrate, and FIG. 22 is a cross-sectional view taken along the line HH in FIG. 21.

1... Picture element electrode, 2, 3... TFT, 4. 5
...Drain Ti electrode, 6.7...Source electrode, 8.
... Source Hass Line, 9... Gate Pass Line,
23.24...Gate electrode, 25'-TazO5 film (gate insulating film), 26-3iNX layer (gate insulating film).

2.

Claims (1)

[Claims] 1. An active device comprising an insulating substrate, pixel electrodes arranged in a matrix on the insulating substrate, and a plurality of signal lines arranged on the insulating substrate. A matrix substrate, wherein at least two thin film transistors are disposed near each picture element electrode, and the at least two thin film transistors are connected in parallel between the picture element electrode and one of the signal lines. active matrix substrate. 2. The active matrix substrate according to claim 1, wherein the gate insulating film of the thin film transistor has at least two laminated layers.