JPH0225307B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a time division multiplex signal modulation system that facilitates clock signal recovery from a differential phase modulated carrier wave on the receiving side when transmitting time division multiplex signals using a differential phase modulation system. (Background of the Invention) When time-division multiplexing N channels of information signals having different clock signal frequencies, a reference clock signal obtained by multiplying the highest frequency among the clock signal frequencies or a frequency higher than the highest frequency by N is used to multiplex the N channels. A time division multiplex signal transmission system has been proposed in which information signals are time division multiplexed and a dummy signal is inserted into a portion where the information signal is insufficient to obtain a continuous time division multiplex signal. Such a time-division transmission system is applied, for example, to multiplexing and transmitting audio signals of multiple channels of PCM satellite broadcasting (where the channels are the number of channels corresponding to the number of video channels). Since the PCM audio signal in satellite broadcasting contains DC components, it is scrambled with a pseudo-random pulse signal (PN signal) and the appearance rate of "0" and "1" is averaged before reception. This makes it easy to reproduce the transmission clock signal from the dibit signal on the side. However, the spectral distribution of low frequency components differs depending on the PCM audio signal, and there is a problem that the data cannot necessarily be considered optimal for a clock regeneration circuit. (Objective of the Invention) The present invention has been made in view of the above, and when transmitting a time division multiplexed signal, especially when transmitting a carrier wave with differential phase modulation, a clock signal is generated from the differential phase modulated carrier wave on the receiving side. An object of the present invention is to provide a time division multiplex signal modulation method that facilitates reproduction. (Structure of the Invention) The present invention converts N channels of information signals having mutually different sampling frequencies or clock signal frequencies into a reference clock obtained by multiplying the highest frequency or a frequency equal to or higher than the highest frequency among the sampling frequencies or clock signal frequencies by N. In the time division multiplex signal system, the signals are time division multiplexed, rearranged in the form of a time division multiplex signal, and the carrier wave is ^2M differential phase modulated by the time division multiplex signal and transmitted.
In the portion where the information signal is insufficient, the input signal at the M input terminals of the phase modulator is a 2M frequency-divided signal of the transmission clock signal. (Operation of the invention) As mentioned above, in the portion where the information signal is insufficient, the transmission clock signal is applied to the M input terminals of the phase modulator.
Since a signal divided by 2M is applied, any output of the phase detector in this part becomes a signal obtained by dividing the transmission clock signal by 2M, and the output with the most number of changing points can be obtained from the ^2M phase detector. . (Examples of the Invention) The present invention will be described below with reference to Examples. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, illustrating the case of W (=2 ^M ) differential phase modulation. Reference numeral 1 designates an input terminal to which the time division multiplexed signal MD time division multiplexed by the above-described time division multiplex signal modulation method is supplied, and 2 designates a clock signal to which the transmission clock signal _BCK of the time division multiplex signal is supplied. Input terminals are shown. The time-division multiplexed signal MD supplied to the input terminal 1 is supplied to the serial input/parallel output converter 3 to be made into a bundle of M bits, and subjected to differential conversion by the M-bit differential modulator 4 in synchronization with the transmission clock frequency. do. The transmission clock signal _BCK is supplied to the frequency divider 5 and divided by 2M to generate a clock signal having a frequency of 1/(2M) (hereinafter referred to as 1/(2M) clock). The data (A ₀ , A ₁ , ...A _M-1 ) differentially converted by the M-bit differential modulator 4 and the 1/(2M) clock (B ₀ , ...B _M-1 ) are sent to the multiplexer 6 . supply 7 is the switching signal SW of multiplexer 6
is the switching signal terminal to which SW is input, and during the period when the dummy signal is inserted during time division multiplex signal generation, that is, the period when the information signal is insufficient, the switching signal SW is input.
The output signal of the multiplexer 6 is (A ₀ ,...,
Switch from A _M-1 ) side to (B ₀ ,..., B _M-1 ) side, W
The signal is supplied to a phase modulator 8 for phase modulation.
In this case, because of the W phase differential phase modulation, M=
From the relationship of log ₂ W, the output of the differential modulator 4 is transmitted during the first M bit period of the information signal portion, as shown in FIGS. 2a and 2b. FIG. 2a schematically shows a time division multiplexed signal MD, where ~T ₁ and T ₃ ~ are information signal parts, and T _1
.about.T3 indicates a portion where a dummy signal is inserted, and FIG. In addition,
In the period T ₂ to _{T 3} in FIG. 2a, the differential modulator 4
The period of M bits during which the output of is selected is shown. Note that 9 is a carrier wave oscillator, and 10 is a ^2M phase carrier wave generator. The carrier wave output from ^{the 2M} carrier wave generator 10 is phase modulated by the output of the multiplexer 6 in the phase modulator 8, and outputted via the bandpass filter 11. FIG. 3 is a block diagram of a demodulator that demodulates a time division multiplexed signal MD from a modulated wave modulated according to one embodiment of the present invention shown in FIG. A modulated wave modulated according to the embodiment of the present invention shown in FIG. 1 is supplied to an input terminal 12 and detected by a ^2M- phase phase detector 13. The output ^M bits of the 2M-phase phase detector 13 are supplied to the ^M -bit difference converter 14, which synchronizes with the clock signal regenerated by the clock regeneration circuit 15 from any one bit of the output of the 2M-phase phase detector 13. Perform differential conversion. Differential converter 1
4 output is parallel input/serial output converter 1
6, it is converted into a serial signal and output. However, the output M bits of the ^2M phase phase detector 13 becomes the same output as the input of the phase modulator 8 in FIG. 1 during the period when the 1/2M clock is detecting the phase modulated signal. Therefore, no matter which bit output of the ^2M -phase phase detector 13 is used as the input to the clock recovery circuit 15, a 1/(2M) clock signal can be obtained. 1/(2M) clock is
2 The output of ^{the M} -phase phase detector 13 has the most points of change. As a result, the number of phase comparison circuits of the PLL circuit in the clock regeneration circuit 15 can be maximized, and the clock signal can be regenerated stably. Furthermore, if special data can be inserted in the time division multiplexing encoder section during the information signal shortage period, the same results as in the above case can be obtained, and the multiplexer 6 in FIG. 1 can be omitted. In particular, in the case of 4-phase DPSK, this can be achieved by using an all-1 bit stream as the above-mentioned special data, eliminating the need for a complicated circuit to insert special data into the time division multiplex encoder section. . Now, in the case of 4-phase DPSK, when all "1"s are inserted as special data, the initial values of the P and Q signals after dibit/difference conversion are P=
0, Q=0, from the phase relationship between the differential conversion signal and the subcarrier shown in Figure 4,

【table】 ‖
The initial value is repeated, alternating between 0 degrees and 180 degrees. Also, if the above initial values are P=1 and Q=1,

[Table] is repeated, and in the same way, 180 degrees and 0 degrees are alternated. Also, if the above initial values are P=0 and Q=1,

[Table] is repeated, and in this case, 90 degrees and 270 degrees are alternated. Also, if the above initial values are P=1 and Q=0,

[Table] will be repeated, and in this case, 270 degrees and 90 degrees will be alternated in the same way. Therefore, when regenerating a clock signal from the output P or Q of the four-phase phase detector 13, the above output P
Alternatively, Q itself becomes a regenerated clock signal. (Effects of the Invention) As explained above, according to the present invention, when a time division multiplexed signal is modulated and transmitted by the differential phase modulation method, 1/(2M) is transmitted during a period when information signals are insufficient.
By inserting a clock, any output of the phase detector during the period when the information signal is insufficient becomes 1/(2M) clock, and it is possible to obtain the output with the most number of changing points from the ^2M phase phase detector. can. Therefore, the number of phase comparisons in the PLL circuit is maximized, resulting in the effect of stabilizing clock signal reproduction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 shows 1/1 in one embodiment of the present invention.
(2M) Schematic diagram showing clock sending timing. FIG. 3 is a block diagram showing the configuration of a demodulator that demodulates a time division multiplexed signal from a modulated wave according to an embodiment of the present invention. FIG. 4 is a diagram showing the phase relationship between the 4-phase DPSK dibit/difference conversion signal and the subcarrier. 3...Serial input/parallel output converter, 4...
M-bit difference converter, 5... Frequency divider, 6... Multiplexer, 8... Phase modulator, 10... 2 ^M -phase carrier wave generator, 11... Bandpass filter.

Claims (1)

[Claims] 1 N channels of information signals having mutually different sampling frequencies or clock signal frequencies are time-division multiplexed using a reference clock signal obtained by multiplying the highest frequency of the sampling frequency or clock signal frequency or a frequency equal to or higher than the highest frequency by N, and In the time division multiplex signal modulation method, in which carrier waves are rearranged in the form of division multiplex signals and transmitted by ^2M differential phase modulation using time division multiplex signals, M phase modulators are used in areas where information signals are insufficient. A time division multiplex signal modulation method characterized in that a signal obtained by dividing the transmission clock signal by 2M is applied as an input signal to the input terminal of the device.