JPH0225573B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a time division multiplexing circuit for time division multiplexing a large number of low speed signals into high speed signals in a time division multiple access satellite communication system.

[Background technology]

In a satellite communication system that uses time division multiple access (hereinafter referred to as TDMA), each participating earth station
TDMA devices time-division multiplex multiple low-speed signals,
on the time axis set on the satellite transponder.
A signal is sent to a predetermined position assigned to the local station in the TDMA frame.

Conventionally, time-division multiplexing of a large number of low-speed signals has been carried out by providing a pulse signal compression circuit for each signal and combining the burst signals output from this circuit. Hereinafter, a conventional time division multiplexing circuit will be explained.

FIG. 1 is a block diagram showing the configuration of a conventional time division multiplexing circuit, and FIG. 2 is a schematic timing chart for explaining its operation. 101,10
2 and 103 are signal input terminals, into which low-speed signals, . . . are input. 1, 2, and 3 are pulse signal compression circuits, which temporally compress the pulses of the low-speed signals , , which are input to each circuit. 4
is a control circuit which specifies a pulse signal compression circuit corresponding to a predetermined low-speed signal according to a port number designation signal inputted from the input terminal 105, and also compresses the pulse signal according to a data gate signal inputted from the input terminal 105. Set the output timing of high-speed signals output from the circuit.

The operation of the circuit according to the conventional example will be explained in more detail with reference to FIG. A in a indicates one frame of TDMA, b is a data gate signal, and c is a port number designation signal. d, e, and f are time slot signals input from the control circuit 4 to the pulse signal compression circuits 1, 2, and 3, respectively, in accordance with the data gate signal b and the port number designation signal c.

The low-speed signal for one frame of TDMA input from the input terminal 101 is sent to the pulse signal compression circuit 1.
The signal is then compressed and stored. Similarly, low-speed signals are also compressed and stored in pulse signal compression circuits 2 and 3, respectively. When a time slot signal is generated in the control circuit 4 using the data gate signal b and the port number designation signal c, (d, e, f),
Depending on the input timing of these signals, burst-like high-speed signals are output from each pulse signal compression circuit. These signals are combined by the OR circuit 5 and output from the output terminal 104 as a time division multiplexed signal set at a predetermined position on one frame.

As explained above, since the pulse signal compression circuit stores the low-speed signal once, a storage circuit is required, and a memory IC called a RAM (Random Access Memory) is usually used.

By the way, when using this memory IC in a pulse signal compression circuit, the required amount of memory generally depends on the speed of the high-speed signal, the operating speed of the memory IC relative to the number of bits for one TDMA frame, and the memory
Determined by the memory capacity of the IC. but
TDMA has a high signal speed after time division multiplexing, the number of bits of the low-speed signal corresponding to one TDMA frame is relatively small, and the storage capacity of the memory IC required is not large (and in recent years memory IC
is rapidly increasing in capacity. ), the quantity of memory ICs tends to be determined by the operating speed of the memory ICs. By the way, memory
The speed of high-speed signals is higher than the operating speed of the IC.
Therefore, the required speed is satisfied by operating the memory IC in a normal manner.

Therefore, if the high-speed signal speed is VMb/s and the operating speed of the memory IC is SMb/s, then n IC memories satisfying the relationship nS≧V (1) are required.
Assuming that the number of low-speed input signals is N, the number of memory ICs required for the entire time division multiplexing circuit is as follows: M=N×n≧V・N/S (2). This shows that the larger the high-speed signal speed V and the number N of low-speed signal inputs are, the larger the number of required memories becomes. TDMA equipment is a communication system suitable for large capacity among systems that simultaneously communicate with a large number of earth stations, so generally the number of low-speed signal inputs N and the high-speed signal speed V are large, and therefore the memory IC used is large.
The number M also becomes very large. As a result, the proportion of the time division multiplex circuit in the TDMA device increases, which is contrary to the miniaturization of the device and also an obstacle to reducing power consumption, which is a drawback of the conventional time division multiplex circuit.

[Purpose of the invention]

The present invention has been proposed in view of the above points, and even when the number of low-speed signal inputs increases or the speed of high-speed signals is large, the memory IC used can be reduced.
The purpose of this invention is to provide a compact, low-power time division multiplexing circuit with a reduced number of circuits.

[Structure of the invention]

The present invention provides a first array conversion circuit that sequentially switches the signal constituent bit strings of a plurality of input low-speed signals bit by bit and converts them into other bit string arrangements, a control circuit, and a first control signal of the control circuit. By dividing the constituent bit string of a low-speed signal, the output signal of the first array conversion circuit is stored by associating the addresses so as to enable simultaneous reading, and the stored signal is transmitted by the second control signal of the control circuit. A plurality of storage circuits are read out in parallel at high speed and are determined by the speed of the high-speed signal and the operation speed of the storage circuit, and a third control signal of the control circuit is output depending on the type of low-speed signal. a second array conversion circuit that converts the array of signal strings read out from the circuit so that the array is the same in units of the low-speed signals; A parallel-to-serial conversion circuit can be provided for outputting to the array conversion circuit.

〔Example〕

Next, the configuration of an embodiment according to the present invention will be described with reference to the drawings. For convenience of explanation, the number of low-speed signals N = 2, the high-speed signal speed V = 16 Mb/s,
It is assumed that the operating speed of the memory circuit is S=8 Mb/s. Since the number n of required memory circuits is n≧2 from equation (1), it is sufficient to use two.

FIG. 3 is a block diagram showing the configuration of a time division multiplexing circuit according to an embodiment of the present invention in that case.

Reference numerals 106 and 107 are input terminals for low-speed signals, respectively, and 6 is a first arrangement conversion circuit that converts the arrangement of constituent bits of the input low-speed signal into a predetermined arrangement. 7 and 8 are first memory circuits, and bit information in the first array conversion circuit 6 is written to a predetermined address position by a memory circuit number designation signal and a write address designation signal output from the control circuit 10. At the same time, the written signal information is read out in parallel as high-speed signals by designating a common read address to the storage circuits 7 and 8 output from the control circuit 10. A second array conversion circuit 9 is controlled by a switching signal from the control circuit 10, and is used to select a terminal to which signals read out in parallel from the storage circuit are to be output. Control circuit 10
outputs the aforementioned memory circuit number designation signal, write address designation signal, and read address designation signal to the storage circuits 7 and 8, and a switching signal to the second array conversion circuit 9, but the output timing of these signals is as follows. It is controlled by a data gate signal and a port number designation signal input via the input terminal 108.

Next, the operation of the embodiment according to the present invention will be specifically explained. FIG. 4 is a diagram of main control signals and a signal state diagram showing in what state the constituent bits of a low-speed signal are arranged or output in each circuit and converted into a high-speed signal. FIG. 4a is a signal state diagram with a low-speed signal, and the number of bits for one TDMA frame is 2m each. When these low-speed signals are input from 106 and 107, respectively, the first array conversion circuit 6 replaces the low-speed signals bit by bit (FIG. 4b). Write address designation signal (fourth
According to Fig. 4c), one side of the signal string in the array conversion circuit 6 (upper side in Fig. 4b) is sequentially outputted and written to a predetermined address position of the first storage circuit (Fig. 4e). upper side). Similarly, one side (lower side in FIG. 4b) of the signal string in the array conversion circuit 6 is sequentially output from the control circuit 10 in accordance with the write address designation signal for the second memory circuit (FIG. 4d). At the same time, it is written to a predetermined address position of the second memory circuit (lower side in FIG. 4e). As can be seen from FIG. 4e, the constituent bits (2m pieces) of the low-speed signal are stored in address numbers 0 to m-1 of memory circuits 1 and 2, and the constituent bits (2m pieces) of the low-speed signal are stored in memory circuits 1 and 2. is stored in address numbers m to 2m-1.

Next, from the input terminal 108, a data gate signal (FIG. 4f) that sets the timing for taking out a high-speed signal from the storage circuit and a port designation signal (FIG. 4g) that instructs switching of the output terminal are input. When the port number designation signal is "1", the read number designation signal is output from the control circuit 10 in the order of address numbers (0 to m-1), and the first storage circuit 7 is output in accordance with this order.
And the operating speed from the second memory circuit 8 is 8 Mb/s.
are read in parallel. For example, when the address number is "0", bit information is stored from the first memory circuit 7.
I ₀ and bit information I ₁ are output from the second storage circuit 8 at the same time, but via separate output signal lines.
When the port number designation signal is “2”, control circuit 1
Readout number designation signals are output in order of address numbers (m to 2m-1) from 0, and signals are read out in parallel from memory circuits 7 and 8 in the same way. However, as shown in Figure 4i, the port number designation signal is "2".
The signal string output from the memory circuits 7 and 8 when
The correspondence with that when the port number designation signal is "1" is exactly the same as the output signal line is opposite.
When the port number designation signal is input to the array conversion circuit 9, the connections of the output signal lines are switched to output high-speed signals in the same order as shown in FIG. 4j.
If necessary, it is also possible to convert the signals into a single string of signals by performing parallel-to-serial conversion. This is done after parallel reading with a conventional pulse compression circuit and synthesis with an OR circuit, and is no different from the conventional one.

Further, when the number N of low-speed signals increases, for example, when N=4, two-input parallel-to-serial conversion circuits can be provided in front of the input terminals 106 and 107 in FIG. 3, respectively. That is, if two low-speed signals are converted into one serial output signal by a two-input parallel-to-serial conversion circuit, the input signals of the first array conversion circuit 6 will be two inputs as in the embodiment. Of course, four port number designation signals are required. In addition, memory circuits 7 and 8
double the storage capacity is required, but the large capacity memory
There is no problem since the IC has appeared.

Even when the high-speed signal speed V increases and many storage circuits need to operate in parallel, the number of storage circuits that can satisfy the high-speed signal speed V (see equation (1))
This number does not change at all even if the number of low-speed signals increases.

Note that although the multiplexing circuit on the transmitting side has been described in the embodiment, the same can be said for the separating circuit on the receiving side. That is, in FIG. 3, when a high-speed signal is applied from the right side, the required low-speed signal is obtained from the left side by going through a completely reverse procedure.

Here, in order to further clarify the effects of the time division multiplexing circuit according to the present invention, we will give specific examples of the number of memory circuits (memory ICs) required when using a conventional circuit and when using the circuit of the present invention. Calculate and compare.

Number of low-speed signals N=40, high-speed signal speed V=60Mb/
The number of memory ICs used in the time division multiplexing circuit of the TDMA device is as follows when the memory IC operating speed S=8 Mb/s and the low-speed signal speed v=1.5 Mb/s.

In the conventional case, from the high-speed signal speed V = 60 Mb/s and the memory IC operating speed V = 8 Mb/s, one pulse signal compression circuit uses 8 memory ICs because 60/8≦8 from equation (1). be done. In the pulse signal compression circuit of an actual TDMA device, two sets of memory circuits are prepared, and when one set writes low-speed signals for one TDMA frame, the other set reads out the signals at high speed, and in the next frame, One set of memory circuits that performed writing performs reading, and the other
The circuit is a double buffer type circuit having two sets of memory circuits that alternate between writing and reading every frame.

Therefore, one pulse signal compression circuit is a memory IC.
8×2=16 pieces are used, and there are 40 circuits in total, so 16×40=640 pieces. This number is only for the multiplex circuit on the transmitting side, and including the separating circuit on the receiving side, the number of memory ICs is 640 x 2 = 1280. On the other hand, in the case of the present invention, the number of memory ICs is high-speed signal speed V = 60 Mb/s, memory IC operating speed S =
Only 8 determined by 8Mb/s are required. The number of low-speed signals N = 40 has a low signal speed v of 1.5 Mb/s, so 8 parallel-to-serial converter circuits convert the signals in 5 columns into 1 column to convert the signals in 8 columns to 1.5 Mb/s x 5 =
If it is converted to a signal with a speed of 7.5 Mb/s, it is sufficient to use a simple array conversion circuit with eight input and output signals. In this case, even if you use the double buffer format and include a separation circuit on the receiving side, 8 x 2 x 2 = 32
Since the parallel-to-serial converter circuit has approximately the same circuit scale as the OR circuit required in the conventional circuit, the effect of the time division multiplex circuit according to the present invention is obvious.

〔Effect of the invention〕

As explained above, the time division multiplexing circuit according to the present invention can dramatically reduce the number of memory ICs used, so it can realize a time division multiplexing circuit that is more compact and has lower power consumption. Signal speed V
When is large, the effect is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional time division multiplexing circuit, FIG. 2 is a schematic timing chart for explaining its operation, and FIG. 3 is a configuration of a time division multiplexing circuit according to an embodiment of the present invention. Figure 4 is a block diagram showing the main control signals and a signal state diagram showing how the constituent bits of the input low-speed signal are arranged in each circuit, output, and converted into a high-speed signal. It is. 1, 2, 3...Pulse signal compression circuit, 4, 10
... Control circuit, 5 ... OR circuit, 6 ... First array conversion circuit, 7, 8 ... Memory circuit, 9 ... Second
array conversion circuit, 101-103, 105-10
8... Input terminal, 104, 109, 110... Output terminal.

Claims (1)

[Scope of Claims] 1. A first array conversion circuit that sequentially switches a signal constituent bit string of a plurality of input low-speed signals bit by bit and converts it into another bit string arrangement, a control circuit, and a control circuit of the control circuit. A first control signal is used to divide the constituent bit strings of one low-speed signal so that they can be read out simultaneously.The output signal of the first array conversion circuit is stored in correspondence with the address, and the stored signal is controlled by the first control signal. a plurality of storage circuits that are read out in parallel at high speed by a second control signal of the circuit, determined by the speed of the high-speed signal and the operating speed of the storage circuit; and the control circuit that is output depending on the type of the low-speed signal. and a second array conversion circuit that converts the array of the signal strings read out from the plurality of storage circuits so that the arrays are the same in units of the low-speed signals according to a third control signal. time division multiplex circuit. 2. The time division multiplexing circuit according to claim 1, further comprising a parallel-to-serial conversion circuit for parallel-to-serial conversion of the plurality of low-speed signals and outputting the parallel-to-serial conversion circuit to the first array conversion circuit.