JPH0225580B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an inter-processor communication system for dividing processors into groups and distributing different types of loads within each group.

Technical background In the load balancing method for multiprocessor systems, for example, when adding the function of a gateway switch for communication processing, which has a connection control function for new service calls such as communication processing services, to a digital TS switch with a multiprocessor configuration, etc. , the control system of a digital TS switch usually consists of a common line signal processing device,
Functions of a signal processing device consisting of a trunk line signal processing device and a call control processing device are distributed via an interprocessor communication control device, and loads are distributed between the signal processing device group and the call control processing device group. One of the call control processing devices serves as a master call control processing device, and a load distribution system is employed which has functions related to the entire system, such as control system configuration management and failure handling.
(For example, Niwa et al.: Digital trunk switch control system configuration research practical application report Vol. 31, No. 5,
May 1982, 929-942, Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation) Conventional technology and problems In the interprocessor communication method for load distribution in multiprocessor systems that has been used in the past, the processor that performs load processing Since the number of groups is limited to one type, there is a drawback that it is not possible to adopt a processing configuration in which multiple types of loads are shared among multiple groups of processors within one multiprocessor system.

OBJECTS OF THE INVENTION The present invention obviates the drawbacks of the prior art by providing means by which a processor requesting communication can specify a group of processors to share the load with, thereby allowing one or more groups of processors to have different types of loads. The drawings will be explained in detail below.

Embodiment of the Invention FIG. 1 is a system configuration diagram of an embodiment of the present invention, in which 1 is an inter-processor communication control device for controlling data transfer, 2 is a control circuit, 3 is a memory section,
4 is a bus coupling circuit, 5a to 5n are processors, 6
is a central control unit, 7 is a main memory unit, 8 is an individual bus,
9 is a common bus. In Fig. 1, the control circuit 2
, memory section 3 , central control section 6 , and main memory section 7
are connected by individual buses 8, and processors 5a-5n are connected by a common bus 9. Individual bus 8 and common bus 9 are connected via bus coupling circuit 4 . The data to be transferred is stored in the main memory section 7 in each of the processors 5a to 5n, and the interprocessor communication control device 1 reads this data and transfers it to the main memory section 7 in the other processors.
Memory-to-memory data transfer is realized by writing again to .

FIG. 2 shows the contents of operands when executing an instruction (hereinafter referred to as SIOF) for registering the number of a group to which a processor belongs in an interprocessor communication control device. In Figure 2, 10 indicates the order information (hereinafter referred to as ODR) that identifies whether the registration is on the sending side or the receiving side, and 11 is the data channel number (hereinafter referred to as ODR).
It's called CHN. ), 12 is the group number (hereinafter referred to as GNO
That's what it means. ) is shown. In this embodiment, the interprocessor communication control device has a data channel interface, and CHN11 is assigned to the interprocessor communication control device. When the SIOF instruction is executed, the contents of the operand are transmitted to the interprocessor communication control device 1 through the individual bus 8 and the common bus 9.

FIGS. 3a, 3b and 3c show examples of the configuration of various control information stored in the main memory 7 of each processor 5a to 5n. In Figure 3a, 13 is a command address word (hereinafter referred to as CAW), 14 is a memory protection key (hereinafter referred to as KEY), and 15 is the storage start address (hereinafter referred to as CMA) of a channel command word (hereinafter referred to as CCW). .) is shown. CAW1
3 is stored at an address within a predetermined system area corresponding to CHN11. Third
Reference numerals 16 and 17 in FIG. 2B indicate a set of CCWs set by the transmitting processor, and a plurality of sets are stored at consecutive addresses starting from the CMA 15 unless otherwise specified. Final
The CCW is connected to the initial value of the CMA 15 by a flag (hereinafter referred to as TIC) 19 for changing the continuity of the CCW, forming an infinite chain. Reference numeral 18 indicates a transmittable display flag (hereinafter referred to as SFLG), 20 indicates the number of transmission data words (hereinafter referred to as WC), and 21 indicates the storage start address of transmission data (hereinafter referred to as DAs). Reference numeral 22 in FIG. 3c is a CCW set by the processor on the receiving side, and like the sending side, it is stored at consecutive addresses unless specified by the TIC 19. CCW2
2 constitutes an infinite chain as on the transmitting side. 23 is a receivable display flag (hereinafter referred to as RFLG), and 24 is the storage start address of received data (hereinafter referred to as RFLG).
It's called DAr. ) is shown. The CCWs 16, 17, and 22 set by the transmitting and receiving processors are prepared for each group in which load distribution is to be performed for both transmission and reception.
This allows a processor to belong to more than one group.

FIG. 4 shows a registration management table (hereinafter referred to as READY table) stored in the memory section 3 of the interprocessor communication control device 1, in which 1 bit of 25a to 25n corresponds to each processor 5a to 5n. READY
Tables are prepared by sender/receiver and group.

Next, the operation of the interprocessor communication control device 1 is
This will be explained with reference to the figures and FIG. There are two types of communication operations: a registration operation 26 and a scan operation 27. The registration operation 26 shown in FIG. 5 is as follows. A processor that performs transmission or reception executes the SIOF command for each group and transmits the group and transmission/reception information to the interprocessor communication control device 1. Interprocessor communication control device 1 is ODR10, CHN1
1. When GNO12 is received, CAW13 is loaded from the predetermined address and sent and received separately.
Register CMA15 in memory section 3 by group,
Furthermore, after setting the processor compatible bit in the READY table to “1”, the condition code (hereafter CDC
That's what it means. ) is returned to the processor. Also the 6th
The scan operation 27 shown in the figure is as follows.
The scan operation 27 is activated periodically using a timer or the like. When scanning is started, one group is first selected. If there is no group to select, the scan operation ends. If a group can be selected, sender and receiver information for each group will be displayed.
The READY table is saved from the memory unit 3 to each register in the control circuit 2. Next, sender READY
Select one processor corresponding to the bit marked "1" in the table. The selection method is, for example, performed cyclically in a predetermined order.
If there is no bit set to "1", it is assumed that all transmission requests within the group in the current scan cycle have been processed, and the next group is selected. If a processor can be selected from the READY table, the corresponding bit in the READY table saved in the control circuit 2 is set to "0", the CCW is loaded from the main memory 7 in the processor, and the TIC is checked. If TIC=
If it is 1, DAs21 is read as the next CCW storage address and a new CCW is loaded. If TIC=0
SFLG18 is checked, and if SFLG=0, it is assumed that there is no transmission request, and the next processor is selected using the READY table. However, in this case, a transmission request is made.
It is assumed that the CCW, that is, the CCW with SFLG=1, is stored continuously. If SFLG=1, the corresponding processor number and CCW are saved in a register in the control circuit 2. Select the receiving processor in the same way and the reception ready status will be displayed.
The CCW and processor number with RFLG=0 are saved in a register in the control circuit 2. Next, based on the information saved in the register, WC data is read from the DAs address in the main memory 7 of the originating processor, and data is sequentially written from the DAr address of the terminating processor's main memory 7, thereby completing the data transfer. Realized. After the transfer is completed, set the RFLG of the used receiving CCW to “1” and set the transmitting CCW to “1”.
The SFLG is set to "0" and stored in the main memory 7 of both processors, and processing proceeds to the next transmission request.

When the internal processing of both processors is completed and they are able to receive and transmit again, CCW16 and 1 are activated.
Together with other information 7 and 22, RFLG and SFLG are rewritten to "0" and "1" by each processor, respectively. That is, the processor on the receiving side rewrites RFLG to "0" when reception is possible, and the processor on the transmitting side rewrites SFLG to "1" when there is data to be transmitted.

In this embodiment, the channel interface of the central control unit 6 is used to control the inter-processor communication control device 1, but the present invention also includes a method of controlling the inter-processor communication control device using other external device control interfaces. It is a mode. In this embodiment, the scan is performed periodically, but the scan may be started immediately after the scan ends. Furthermore, the method for selecting transmitting and receiving processors and the method for selecting groups, such as random sampling, is not limited to this embodiment and can be applied to the present invention.

Effects of the Invention As explained above, according to the present invention, if each processor sets a series of CCWs for each group and for each transmission and reception, the inter-processor communication control device detects transmission requests within each group and selects an incoming processor. Since the data transfer is performed by the processor, if the content of the transferred data is used as a processing request to other processors, the load can be shared by group. For example, if the present invention is applied to a switch control device, a processor group that performs call control for telephone services and a processor group that performs call control for non-telephone services are incorporated into the same multiprocessor system, and input/output is performed for the two services. This has the advantage that it is possible to share the load within the group by service type while sharing devices, signal processing devices, etc.

[Brief explanation of drawings]

Figure 1 is a system configuration diagram of an embodiment of the present invention, Figure 2 is the operand configuration of the SIOF instruction, Figure 3 is a,
b and c are the configurations of various control information stored in the processor, FIG. 4 is the configuration of the registration management table, FIG. 5 is a registration operation flowchart of the inter-processor communication control device, and FIG. 6 is the inter-processor communication control device. This is a scan operation flowchart. DESCRIPTION OF SYMBOLS 1... Inter-processor communication control device, 2... Control circuit, 3... Memory section, 4... Bus coupling circuit, 5
a to 5n...Processor, 6...Central control unit, 7
... Main memory, 8 ... Individual bus, 9 ... Common bus, 10 ... Sending side, called side registration identification order information (ODR), 11 ... Data channel number (CHN),
12...Group number (GNO), 13...Command address word (CAW), 14...Memory protection key (KEY), 15...Storage start address (CMA), 16, 17, 22...Channel command word (CCW), 18...Sendable display flag (SFLG), 19...Channel command word (CCW)
flag to change the continuity of (TIC), 20
... Number of transmitted data words (WC), 21 ... Storage start address of transmission data (DAs), 23 ... Receivable display flag (RFLG), 24 ... Start storage address of received data (DAr), 25a to 25n... ...1 bit, 2 corresponding to each processor 5a to 5n in the registration management table
6...Register operation, 27...Scan operation.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system in which a plurality of processors are each connected via a bus to an interprocessor communication control device that controls communication between the processors, the plurality of processors are divided into a plurality of groups. , and each of the processors belongs to one or more of the groups, and the processor is registered according to a registration instruction that includes an identification number of the processor, a group to which the processor belongs, and information indicating whether it is a receiving side or a transmitting side. , means for notifying the inter-processor communication control device of an identification number of the processor, a group to which the processor belongs, and information indicating whether it is a receiving side or a sending side, and setting a transmittable flag when there is sending side data. , means for setting a receivable flag when the received data storage area is empty, the inter-processor communication control device comprising: a registration management table that displays the receiving and transmitting processors for each group; and the registration command. means for registering the processor in the registration management table as a receiver or a sender in the group indicated in the registration command when receiving a notification from the processor; Select one of the processors on which the side display is being performed, check whether the transmittable flag of that processor is set, and when the transmittable flag is set, select one of the registered receiving side processors from the registration management table. After that, it is checked whether the receivable flag is set in the receiving processor, and when the receivable flag is set, the selected transmitting processor and receiving processor are selected at a uniform rate. An inter-processor communication method comprising means for transferring transmission data between processors.