JPH02256321A - Asynchronous counter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

This invention is a gate array LSI (large scale integrated circuit)
The present invention relates to an asynchronous counter in the field of technology, etc., and particularly relates to an asynchronous counter that synchronizes a manually inputted clear signal.

[Conventional technology]

In a gate array LSI, a clear signal is input asynchronously to a clock signal in an asynchronous counter made up of logic gates.

[Problem to be solved by the invention]

However, in order for the flip-flops that make up the Moeki counter to output stable data, a predetermined hot-up time and hold time are required, so if the clock signal and clear signal are input manually at almost the same time, , the operation of the flip-flop became unstable, causing malfunction. The present invention was made to eliminate the above-mentioned problems, and an object of the present invention is to provide an asynchronous counter that eliminates malfunctions by synchronizing a clear signal with a clock signal.

[Means to solve the problem]

The asynchronous counter of this invention is a gate array LSI.
An asynchronous counter composed of logic gates, characterized in that it is provided with a signal synchronization circuit that synchronizes a clear signal input to the asynchronous counter with a clock signal at a predetermined timing. do.

[Effect]

For example, if the above signal synchronization circuit delays the clear signal and synchronizes it with a clock signal of opposite phase,
The input clear signal is 180 degrees higher than the original clock signal.
Since a phase delay occurs and a sufficient time difference is provided between the input of the clock signal and the clear signal, normal operation of the asynchronous counter is guaranteed.

【Example】

FIG. 1 is a circuit diagram showing an embodiment of an asynchronous counter of the present invention. The clock signal CK is input to the CKB terminal of the asynchronous counter 1 and the D-type flip-flop circuit (hereinafter abbreviated as FF) 3, and the clock signal CK inverted via the inverter 2 is input to the CK terminal of the FF 3. The clear signal CLR is input to the D terminal of the FF 3 via an RS latch circuit composed of two NAND circuits 4.5, and is also input to one input section of another NAND circuit 6. FF circuit 3 is connected to the other input section of 6.
The output signal from the Q terminal of is input. Further, the NAND output of this NAND circuit 6 is given as a trigger signal T to the RS latch circuit. Then, the output signal from the QB terminal of the FF circuit 3 is sent out as a clear signal of the asynchronous counter l. The operation of the asynchronous counter having the above configuration will be explained with reference to the timing chart of FIG. Initially, the FF3 is in a reset state, and the Q terminal outputs, and the QB terminal output becomes H. Therefore, the NAND circuit 6 outputs H as the trigger signal T. When clear signal CLR is H and trigger signal T is H, R
The S latch circuit outputs a signal, and the D terminal input of FF3 is at L level. In this state, when the clock signal C1 is L (at this time, the GK terminal input of F'F3 is l-1), when the clear signal CLR changes from H to L (at the time to, the F-th point from the D terminal manual ladder). After that, in FF3, when the CK terminal input rises from L to H, that is, when the inverted clock signal CK, which is the OK terminal input, falls (time 11), the QB terminal switches from H to L, and the asynchronous counter The clear signal to 1 becomes active, and the Q output terminal outputs H. After that, the clear signal CLRh (
When the level changes from L to H (time t4), the NAND circuit 6 outputs L as the trigger signal T, so the D terminal input changes from H to L. After that, when the GK terminal power rises (at time H), the clear signal CLR to the asynchronous counter I becomes inactive, the output terminal Q becomes L, and the trigger signal T from the NAND circuit 6 becomes H. Next As shown in the timing chart in Figure 3, the clear signal CLR falls when the clock signal GK is L (time 1+), and the clear signal CLR rises at time t immediately after the next rise of the clock signal GK. In this case as well, the D terminal power changes from L to 11 at time I, and the Q terminal output switches to H at the next rising edge of the CK terminal power (time ts). At this time, the clear signal CLR is Since it has already become H, the trigger signal T from the NAND circuit 6 changes from tf to L. At the next rising edge of the GK terminal input (time ts), FF3 is reset, and the QI3 terminal output becomes
Since the Q terminal output becomes L, the trigger signal T becomes H,
Q terminal output becomes L. As can be seen from the above operation example, the clear signal output from the D-type flip-flop circuit is outputted with a phase shift of 180° from that of the clock signal with respect to the original clear signal. [Effects of the Invention] As explained above, the present invention prevents the clear signal and the clock signal from being input at the same time so that the hot up time and bold time required for normal operation of the counter are sufficiently satisfied. Since the clear signal is input at a predetermined timing with respect to the clock signal, malfunctions in the counter can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the asynchronous counter of the present invention, and FIGS. 2 and 3 are time charts showing the operation of the circuit of FIG. 1. ■...Asynchronous counter 2...Inverter, 3...D type flip-flop circuit, 45.6...NAND circuit.

Claims (1)

[Claims] (1) An asynchronous counter composed of logic gates in a gate array LSI, which includes a signal synchronization circuit that synchronizes a clear signal input to the asynchronous counter with a clock signal at a predetermined timing. This is an asynchronous counter.