JPH03218112A - Register circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a register circuit that prevents write errors to a D-type flip-flop.

BACKGROUND OF THE INVENTION In recent years, semiconductor integrated circuits have become highly integrated, causing delays due to loads inside the semiconductor integrated circuits, which can cause malfunctions.A conventional register circuit will be described below.

FIG. 2 shows the configuration of a conventional register circuit.

In FIG. 2, 1 is an inverter that inverts the clock signal, and 2 is a NAND gate that performs the logical product negation of the output of the inverter 1 and the write signal. 3 is a D-type flip-flop which inputs the output of the NAND gate 2 to its clock terminal.

The operation of the register circuit configured as described above will be explained below.

First, in the circuit shown in FIG. 2, the write signal is normally switched when the clock signal is at a high level, and if the write signal is enabled, it is synchronized with the clock signal by the NAND gate of FIG. When the clock signal is at a low level, a pulse is generated at the clock terminal of the D-type flip-flop to write data at the data input terminal. Further, when the write signal is disabled, no pulse is generated after the clock signal becomes low level, and the previous data is retained.

Problems to be Solved by the Invention However, in the conventional configuration described above, when a phase shift occurs in the clock signal, a phenomenon occurs in which the write signal is switched when the clock signal becomes low level. When the above phenomenon occurs, the write signal is disabled even though it is originally disabled.
There was a problem in that a pulse was generated at the clock terminal of the D-type flip-flop shown in the figure, and the contents of the D-type flip-flop were rewritten.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a register circuit that prevents write errors in a D-type flip-flop even if a phase shift of a clock signal occurs.

Means for Solving the Problems To achieve this object, the register circuit of the present invention has D.
Provide a selector consisting of two AND gates and one OR gate at the data input of the type flip 7 flop. The input signal and the harm signal are input to one AND gate of the selector, and the output signal of the D-type flip-flop and the inversion of the write signal are input to the other AND gate.
The configuration is such that the clock signal and write signal are independent.

Effect: With this configuration, it is possible to prevent write malfunctions in which the contents of the D-type flip-flop are rewritten even when a phase shift of the clock signal occurs.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of a register circuit in an embodiment of the present invention.

In FIG. 1, 10 is a D-type flip-flop, 11 is an inverter that inverts the write signal, 12 is an AND gate that inputs the output of the inverter 11 and the output of the D-type flip-flop 10, and l3 is a data input. An AND gate for inputting a signal and a write signal, 14 is the above-mentioned 1
This is an OR gate that inputs the outputs of AND gates 2 and 13. The output of the above-mentioned 14 OR gates is inputted to the D terminal of the above-mentioned 10 D-type flip-flop.

A clock signal is also input to the clock terminal of the D-type flip 7-lop.

The operation of the register circuit configured as described above will be described below.

When writing the data of the data input signal to the D-type flip-flop, the write signal becomes high level, and the AND gate 13 outputs the level of the data input signal by multiplying it with the data input signal. Further, since the inverted level of the write signal is inputted to the AND gate 12 by the 1L inverter, the output is always at a low level regardless of the output of the D-type flip-flop 10. 12 and 13
With the output of the AND gate, the 14 OR gate becomes 13
The output of the AND gate, that is, the data input signal is 10
output to the D terminal of the D-type flip-flop. A D-type flip-flop is a falling edge of a clock signal.
Write input data.

Further, when data is not written, the write signal becomes low level, and the AND gate 13 outputs a low level regardless of the data input signal. Further, the AND gate 12 receives the high-level signal obtained by inverting the write signal by the inverter 11, and therefore outputs the output signal level of the D-type flip-flop 10. Based on the outputs of AND gates 12 and 13, OR gate 14 outputs the output signal of 12 AND gates, that is, the output signal of 10 D-type flips and 7 lops. The D-type flip 7 lop writes the output signal on the falling edge of the clock signal.

As in the above embodiment, by providing a selector composed of two AND gates and one OR gate for the input signal and output signal of a D-type flip-flop, and switching by a write signal, the phase of the clock signal is Write malfunctions due to misalignment can be prevented.

Effects of the Invention As described above, the present invention includes a selector composed of two AND gates and one OR gate at the D input of a D-type flip-flop, and one AND gate receives a human input signal and a write signal, and the other By inputting the output signal 7 of the D-type flip 7 lob and the inversion of the write signal to the AND gate, and making the clock signal and write signal independent, it is possible to prevent write malfunctions of the D-type flip 7 lob. , extremely useful.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a register circuit in an embodiment of the present invention, and FIG. 2 is a circuit diagram of a register circuit in a conventional embodiment. 10...D type flip-flop, 11...
...Inharta, 12.13...And gate, 14...Or gate.

Claims (1)

[Claims] The data input of the D-type flip-flop is equipped with a selector consisting of two AND gates and one OR gate.
One AND gate receives the input signal and write signal,
A register circuit that inputs the output signal of the D-type flip-flop and the inverted write signal to the other AND gate, and prevents write malfunctions of the D-type flip-flop by making the clock signal and the write signal independent.