JPH02257251A - Information processor - Google Patents

Abstract

PURPOSE:To monitor which CPU and access to be executed cause the generation of abnormality by monitoring a bus master for occupying a common bus as a position of a third person. CONSTITUTION:A 1-chip central processing unit 3 measures a time interval of a transfer response for showing a fact that a bus request from an OR input part 1 and an access are ended, and in the case when its time interval is longer than the time of a normal time determined in advance, an address 6, data 7, commands 8 - 11, a bus request and a but priority input 12 in that case are divided and inputted through a multiplexer part 2. Subsequently, a module of the CPU 3 in which abnormality is caused is decided from the bus request, and from information of the address 6, the data 7 and the commands 8 - 11, error information such as which data 7 is brought to memory write or input/ output write to any address 6, and which data is brought to memory read or input/output read is obtained, worked and informed. In such a way, even if the bus master is brought to stall, bus time-out can be detected, and abnormality information is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to an information processing device configured with multiple CPUs. The present invention relates to monitoring of a bus master in an information processing apparatus equipped with a CPU dedicated to monitoring the bus master from the standpoint of a third party.

〔overview〕

The present invention detects a bus timeout even if the bus master stalls by monitoring the bus master occupying the common bus from a third party's perspective in an information processing device in which a plurality of CPUs are connected by a common bus. This makes it possible to monitor which CPU is attempting to perform what kind of access and whether an error has occurred.

[Conventional technology]

Conventionally, Intel MULTIBUS (IEEE796) is a bus that can use this type of multi-CPU configuration. Although it provides a means to arbitrate the shared bus,
There is no third-party monitoring means to monitor the bus master occupying the shared bus, and the bus master uses a timer to detect an abnormality in which the bus master occupies the shared bus for a long time in the form of a bus timeout.

[Problem that the invention seeks to solve]

In the conventional bus master monitoring described above, the CPU that becomes the bus master monitors the bus occupancy time, so if a shared input/output device or shared memory is accessed through the shared bus, there is no risk of failure of the shared input/output device or shared memory. When there is no transfer response due to the cause and the bus occupancy continues for a long enough time to be considered abnormal, the bus master is normal and the abnormality can be detected as a bus timeout. However, if the local memory in the bus master malfunctions or the program If a shared input/output device or a shared memory is accidentally accessed due to runaway, the bus timeout may not be detected because the CPU in the monitoring position is not operating normally.

The present invention aims to eliminate such drawbacks, and aims to provide a device that can detect a bus timeout even when a shared input/output device or shared memory is accessed due to a local memory failure or program runaway in the bus master. do.

[Means for solving problems]

The present invention provides an information processing apparatus in which a plurality of central processing units are connected by a common bus, including a logical sum input unit for manually inputting a bus request requesting that a module of each central processing unit become a bus master, and an address, data, and , memory command, memory write command, input/output command,
measuring the time interval between the bus request from the bus request and the transfer response indicating that the access has been completed; If the time is longer than a predetermined normal time, the address, data, command, bus request, and bus priority input of that bird are input through the multiplexer section, and the module of the central processing unit that caused the abnormality is determined from the bus request. Then, from the address, data, and command information, determine what data was written to memory or written to which address.
The present invention is characterized by comprising a bus master monitoring means including a one-chip central processing unit that obtains, processes, and notifies error information regarding which address an attempt is made to read memory or read input/output.

[Effect]

The one-chip central processing unit measures the time interval between the bus request from the OR input unit and the transfer response indicating that the access has ended, and if the time interval is longer than the predetermined normal time, the time interval is Addresses, data, commands, bus requests, and bus priority inputs are divided manually through the multiplexer section, the module of the CPU that caused the error is determined from the bus requests, and which address is assigned based on the address and data command information. Obtain, process, and notify error information such as what kind of data was written to memory or input/outputted, and which address was attempted to be read from memory or read from human output.

This makes it possible to detect a bus timeout even if the bus master stalls, and to obtain abnormal information such as which CPU is attempting to become the bus master and which CPU is attempting to perform what kind of access when an error occurs. can.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart of the embodiment of the present invention when the bus is abnormal and when it is abnormal.

The embodiment of the present invention uses a bus request (B RE Qii=Q,
1.2, )4 logical sum input part 1 and address x (AD
Rn n=o, 1.2, )6, data (DATmm=
0.1.2, )7, Memory read command (MRDc
) 8, Memory write command (MWTc) 9, Output card command (IORc) 10, Output card command (IOWcHL bus request (BREQi = Q, 1
．． 2. ) 4. CP with the highest priority among bus requests
A multiplexer unit 2 divides the bus priority input (BPRNii=0.1.2,...) 12 that gives permission to the U module to use the bus into eight port inputs, and a bus request (BR
EQi) 4 and a transfer response (
XACK) 50 hour intervals, and if it is longer than the predetermined normal time, the address at that time (A
DRn) 6, data (DATm) 7, each command (M
RDc, MWTc, l0Rc, 10Wc) 8.9
．． 10.11, manually input the bus request (BREQi) 4 and bus priority input (BPRNi) 12 through the multiplexer unit 2, determine the CPU module that caused the abnormality from the bus request (BREQi) 4, and input the address, data, and command. ROM, RAM, input/output information that obtains, processes, and reports error information such as what kind of data was written to memory or input/output to which address, and what address was attempted to be read from memory or input/output. The bus master monitoring means includes a one-chip CPU incorporating an output port and a timer on one chip.

A logical sum (hereinafter referred to as OR) input unit 1 takes the OR of bus requests (BREQi) 4 from each CPU module, and a multiplexer 2 outputs the address (A D Rn) 6 and data (
DATn)? , memory read command (MRDC) 8,
Memory write command (MWTc) 9, crowd control command (IORc) 10. Input/output Kalide command (
IOWc) 11, bus request (BREQi) 4, and bus priority input (BPRNi) 12 signals as the selection signal (SELE).
CT) 13 to select in units of 8, 1 chip CPU
Divide and input into 3 input ports.

The 1-chip CPU 3 monitors the OR of the bus request (BREQi) 4, and any CPU module responds to the bus request (BREQi).
When BREQi)4 is turned on, a transfer response (XACK) indicating that the bus master access has ended from that point on.
If the transfer response (XACK) 5 does not turn on within a predetermined normal time, it is assumed that some abnormality has occurred, such as accessing non-existent memory or input/output. It makes a judgment and takes in various information from the multiplexer 2.

Various information includes the address (AD) at the time the abnormality was detected.
Rn) 6, data (DATn) 7, memory read command (MRDc) 8, memory write command (MWTc)
9, Input/output command (IORC) 10, Input/output command (I0WC) 11, Bus request (BREQ)
i) 4, the bus priority input (BPRNi) is in the state of 12.

From bus request (BREQi) 4, bus priority input (BPRNi) 1 indicates which CPU module is issuing a bus request in an attempt to become the bus master, and whether or not it has been granted.
You can judge by 2. Next, the CPU module that became the bus master reads data from or writes data to which memory or input/output address, address (ADRn) 6, data (DATn) 7, memory! J-)': I7 command (MRDc) 8, memory write command (MWTc) 9, input/output command (I
ORc) and input/output command (IOWc) 11.
ATO~DAT7)14,! J-t' (RD)15
．． 5a) (WR)16, Chip Select (C3
) 17, address (AO) 18, and interrupt (INT) 19 can also be used to notify the upper CPU.

FIG. 2 shows a timing chart for writing data to the memory, with solid lines in normal times and dotted lines in abnormal times. When a CPU module that wants to become a bus master turns on bus request (BREQI) 4, it compares the priority with other bus requests and if it has the highest priority, the bus priority input (BPRNi) indicates permission for the bus request. 12 is turned on, address (ADRn) 6, data (DATm)? , memory write command (MWTC) 9 can be output to the shared bus.

When data (DATm) 7 is written to the memory selected by address (ADRn) 6, transfer response (XACK) 5 is turned on by the memory module, bus request (BREQi) 4, and bus priority input (B P RN1).
12. Memory write command (MWTc) 9 is turned off, address (A D RD) 6, data (DATm)
7 will also be released. In the event of an abnormality, the transfer response (XACK) 5 is not turned on even after a certain period of time has elapsed, and the shared bus remains occupied.

〔Effect of the invention〕

As explained above, according to the present invention, by having a single-chip CPU monitor the bus status from a third party's perspective, it is possible to solve the problem of not being able to detect a bus timeout due to the bus master stalling. This has the effect of being able to obtain information such as which CPU module is attempting to perform what kind of access when an error occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart of the bus in normal and abnormal states according to the embodiment of the present invention. 1... Logical sum (OR) input section, 2... Multiplexer, 3... 1-chip CPU, 4... Bus request (BR
EQii=Q, 1.2, -...), 5... Transfer response (
XACK), 6...address x (ADRn n=o
, 1.2, -), 7-...Data (DATmm=O1
1, 2,...) 8...Memory read command (MR
Dc), 9...Memory write command (MWTc),
10... Input/output card command (IORc), 11.
...I/O Kalide command (IOWc), 12...Bus priority input (BPRNi i=0.1.2,...
), 13...SELECT, 14...Data (DATO~DAT?), 15...Read (RD
), 16...Write (WR), 17...Chip select (C3), 18...Address (AO),
19...Interrupt (INT).

Claims (1)

[Scope of Claims] 1. In an information processing device in which a plurality of central processing units are connected by a common bus, a logical sum input unit that inputs a bus request requesting that a module of each central processing unit become a bus master; , bus master monitoring means including a multiplexer section that divides information on the bus into port inputs, and a one-chip central processing unit that obtains, processes, and notifies monitoring information from the logical sum input section. Information processing equipment.