JPH02260459A - Input protective circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an input protection circuit, and more particularly, to an input protection circuit in a semiconductor device with a thin film SOI structure that can be applied to a three-dimensional IC, etc. [Prior Art] Generally, an MO8 type Semiconductors are designed to operate under a certain low voltage, so when connecting this MO8 type semiconductor to an external circuit, it is necessary to provide an input protection circuit to prevent surge current from being applied to the internal circuit. There is. For this reason, general LSIs are provided with an input protection circuit as shown in FIG. 4, and the diode characteristics of the PN junction in Tr□ (transistor 1) are used to prevent surge current from being applied to the internal circuit.

On the other hand, SOI (Silicon-On-Insul
Due to its structure, the MOS transistor with the ator structure has the following characteristics:
It has features not found in ordinary single crystal silicon, such as latch-up free, soft error resistance, and low stray capacitance.Also, by making the active layer sufficiently thin, SOI
It was devised to remove the #klo phenomenon, which was a drawback of the structure, and to obtain high mobility by lowering the impurity concentration of the substrate (°C
Institute of Electronics, Information and Communication Engineers SDM-1, 54). This input protection circuit is not of SOI structure.

-This is a simple input protection circuit. And such a thin film S
As an input protection circuit for a semiconductor device having an OI structure, for example, Japanese Patent Laid-Open No. 12364/1983 proposes an input protection circuit using an input resistor and a gated diode structure transistor.

However, in these conventional input protection circuits,
Since the input protection circuit section is also formed using the same process, the impurity concentration of the transistor substrate is low.
The reality is that no PN junction is formed, and therefore an input protection circuit cannot be created using a method such as a normal single crystal.

(Objective) The present invention provides an input protection circuit that has an effective function even in an element having an SOI structure.

[Structure] The present invention provides an input protection circuit that is provided as a branch in the middle of the power supply line to the internal circuit in a circuit with a thin film SOI MO8 structure. providing an impurity region;
Alternatively, (b) the active layer of the N-ch transistor of the input protection circuit is thicker than the active layer in other regions.

The present inventors have conducted various research and examinations regarding input protection circuits, and have found that either a P-type impurity region is provided only in the active layer in the channel region of the input protection circuit, or a By making the active layer thicker than the active layer in other regions, a latch phenomenon occurs in the input protection circuit section.

It was discovered that a current exceeding the rated value does not flow into the internal circuit.The present invention was made based on this knowledge.

FIG. 2 shows a cross-sectional configuration of an N-ch transistor having an SOI structure. In the figure, 1 is an insulating substrate, 2 is a source/drain diffusion layer, 3 is a substrate (active layer), 4 is a gate oxide film, 5 is an insulating film between the eyebrows, and 6 is a metal electrode. In such an N-ch transistor, when the substrate is placed in a floating state, holes due to the "impact ionization phenomenon" generated near the drain are accumulated in the substrate, causing a hysteresis phenomenon as shown in Figure 3. generate.

This hysteresis phenomenon occurs suddenly when the drain voltage exceeds a certain voltage (due to positive feedback). The characteristic curve in Figure 3 shows that the drain voltage = 15 volts,
■=11 volts.

This is the case where ■=9 volts, ■=7 volts, and ■=5 volts. The mechanism is explained as follows.

(i) An "impact ionization current" generated near the drain flows from the substrate toward the source, increasing the potential of the substrate. (■) The threshold voltage (Vth) decreases due to the increased substrate potential. (hear)
The drain current further increases due to the decrease in Vth. (
tv) The increased drain current further increases the "impact ionization current".

Analysis of this mechanism shows that the resistance value of this element decreases rapidly when a drain voltage of a certain level or higher is applied. This element is used to form an input protection circuit.

FIG. 1 shows a circuit diagram of an input protection circuit according to the present invention. In FIG. 1, the drain electrode of the N-Ch transistor is connected to the input batto internal circuit line, and the source electrode and gate electrode are connected to the GND terminal. Also,
The resistor R is provided to prevent a current exceeding the rated value from flowing into the input protection circuit.

As described above, in the present invention, (a) a P-type impurity region is provided only in the active layer in the channel region of the input protection circuit, or (b) the film thickness of the active layer of the N-ch transistor of the input protection circuit is reduced. The active layer is made thicker than the active layer in other regions.

Here, typical manufacturing methods for these means (a) and (b) will be explained.

Means for (a) The active layer is LP-shaped as in a normal SOI structure transistor.
The film is formed by CVD method. At this time, as described above, the film thickness is set to be 800 Å or less. Next, after forming a gate insulating film by thermal oxidation or CVD, B0 ions are implanted only into the active layer of the input protection circuit section. Subsequently, a gate electrode is formed by a CVD method and patterned, and then a source and a drain portion are formed by an ion implantation method.

If this method is used, the latch phenomenon will not occur in elements other than the input protection circuit section due to the effect of thinning the layers described above, but
In the input protection circuit section, since the channel is doped, a complete layer does not extend from the gate, so holes are accumulated and a latching phenomenon occurs.

Means of (b) Similar to the means of (a) above, an active layer is formed by LPCVD (thickness enough to cause a latch phenomenon: about 1,500 layers), and the parts other than the input protection circuit are etched to form a latch. The layer will be thinned to a thickness of about 800 people (approximately 800 people) that will not cause the phenomenon. After that, a gate insulating film, a gate electrode, and a source and drain portion are formed.

If this method is used, only the input protection circuit portion is thick and a latch phenomenon occurs there.

Examples are shown below.

Embodiment 1 This embodiment describes an input protection circuit according to the means (a).

An active layer is formed on an insulating substrate (quartz) using the LPCVD method to a thickness of about 1000, and patterned into an island shape. next,
Approximately 1,000 gate oxide films are formed using a thermal oxidation method. Mask the area other than the input protection circuit section using a resist, and apply B'' (24KaV) only to the active layer of the input protection circuit section.
Dose amount I.

E-13) Inject to make the substrate P-type. Gate electrode L
A film is formed using the PCVD method (3000 people) and patterned.

Using the gate electrode, source and drain electrodes are created by ion implantation using the self-line method. Interlayer insulation film L
After forming a film with a thickness of approximately 1000 μm using the PCVD method, contact holes were formed, AQ electrodes were formed (approximately 1 μm) and patterned, and a passivation film (SiN4) was deposited with a thickness of approximately 1 μm.
A film is formed to a thickness of μ brass using the P-CVD method, and finally the electrode pads are opened.

Embodiment 2 This embodiment describes an input protection circuit using the means (b) above.

An active layer is formed to a thickness of approximately 1000 nm on an insulating substrate (quartz) using the LPCVD method, and is patterned into an island shape in the 9th step.
Only the input protection circuit section was masked with resist and dry etched.

Etch the other active layer to about 1000 people.

Thereafter, in the same manner as in Example 1, the process started with forming a gate oxide film using the thermal oxidation method and ended with the process of opening the electrode pads.

【effect〕

According to the input protection circuit according to the present invention, when the input voltage is higher than the power supply voltage VQD, the voltage is applied to the drain of the N-ch transistor of the input protection circuit, so that an "'impact ionization phenomenon" occurs. Threshold voltage (lh)
becomes low and the transistor turns on, so
The resistance between VD[1 and GND becomes low, and the input current quickly flows to the GND terminal and does not flow into the internal circuit. In other words, the effect of an input protection circuit is brought about.

If the input voltage is lower than the power supply voltage, the input protection circuit N-
The gate electrode of the chh transistor is connected to GND and is therefore in an OFF state. Therefore, the input power does not flow to this transistor, but instead flows to the internal circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input protection circuit according to the present invention. FIG. 2 is a cross-sectional view of the SOI element. FIG. 3 is a hysteresis curve diagram of the SOI element shown in FIG. 2. FIG. 4 is a circuit diagram showing a conventional single crystal silicon input protection circuit. 1... Insulating substrate 2... Source (S)/drain (D) diffusion layer 3...
Substrate (active layer) 4...Gate oxide film 5...Interlayer insulating film 6...Metal electrode patent applicant Rico Co., Ltd. - Procedural amendment May 3, 1989 Applicable Commissioner of the Patent Office Yoshi 1) Text Tsuyoshi Tono 1, Indication of the case 3゜Relationship with the case of the person who amends the input protection circuit Patent applicant 1-3-6 Nakamagome, Ota-ku, Tokyo No. 4 Figure 6 Contents of the amendment (1) Specification No. 3 Page 2-9 lines “This input protection circuit...
...(snip)...It was proposed. ” is corrected to the following wording. ``However, the human power protection circuit used in this is SOI
Not for structural use, but for ordinary (for example, JP-A-58-1
No. 2364) This was an input protection circuit using an input resistor and a transistor with a gated diode structure. (2) On page 8, line 14, "quartz" is corrected to "glass." (3) Page 8, lines 19-20 r1. Correct E-13J to rlE-13J. On page 9, line 14, "quartz" is corrected to "glass." Figure 2 of the drawings has been corrected as shown in the attached sheet. List of attached documents

Claims (1)

[Claims] 1. In an input protection circuit provided as a branch of a power supply line to an internal circuit in a circuit with a thin film SOIMOS structure, a P-type impurity region is provided only in the active layer in the channel region of the input protection circuit. An input protection circuit characterized by providing an input protection circuit. 2. In an input protection circuit that is provided as a branch of the power supply line to the internal circuit in a circuit with a thin-film SOIMOS structure, the active layer of the N-channel transistor in the input protection circuit is thicker than the active layer in other areas. An input protection circuit characterized by: