JPH02260667A - Compound semiconductor solar cell on silicon substrate and manufacture thereof - Google Patents
Compound semiconductor solar cell on silicon substrate and manufacture thereofInfo
- Publication number
- JPH02260667A JPH02260667A JP1083278A JP8327889A JPH02260667A JP H02260667 A JPH02260667 A JP H02260667A JP 1083278 A JP1083278 A JP 1083278A JP 8327889 A JP8327889 A JP 8327889A JP H02260667 A JPH02260667 A JP H02260667A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- insulating film
- silicon substrate
- conductivity type
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、GaAs等の化合物半導体をSi基板上に
形成してなる太陽電池およびその作製方法に関し、特に
Si基板上にGaAs太陽電池を複数個接続する際の特
性劣化を抑えるための電池構造の改良を図ったものに関
する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a solar cell formed by forming a compound semiconductor such as GaAs on a Si substrate and a method for manufacturing the same, and particularly relates to a method for manufacturing the same, in which a plurality of GaAs solar cells are formed on a Si substrate. This invention relates to an improved battery structure for suppressing characteristic deterioration when connecting individual batteries.
〔従来の技術]
第2図は従来方法により製造したSi基板上GaAs太
陽電池の接続方法を示す断面図であり、図において、1
はSi基板、2はn型G a A s層、3はp型Ga
As層、4はp型A l o、 ssG a o、 +
sAs窓層、5はS i 3 N−反射防止膜、6はp
型電極、7はn型電極、8は溶接用パッド、9はインタ
コネクタである。[Prior Art] FIG. 2 is a cross-sectional view showing a method of connecting a GaAs solar cell on a Si substrate manufactured by a conventional method.
is a Si substrate, 2 is an n-type GaAs layer, 3 is a p-type Ga
As layer, 4 is p-type A lo, ssG a o, +
sAs window layer, 5 is S i 3 N- antireflection film, 6 is p
7 is an n-type electrode, 8 is a welding pad, and 9 is an interconnector.
この従来のGaAs太陽電池は、Si基板1上にMOC
VD法によりn型GaAs層2.P型GaAs1i3.
P型Alo、ssG ao、15A S窓層4を順次形
成する。そして、5izN、反射防止膜5を全面に形成
する。次に、p型A l 6. ssc a o、 +
sAs窓層4.’Si、N4反射防止膜5の所要箇所を
開孔し、p型電極6および溶接用パッド8を形成し、最
後にn型電極を基板裏面に形成することにより得られる
。This conventional GaAs solar cell has an MOC on a Si substrate 1.
An n-type GaAs layer 2. is formed by the VD method. P-type GaAs1i3.
P-type Alo, ssG ao, and 15A S window layers 4 are sequentially formed. Then, an antireflection film 5 of 5 izN is formed on the entire surface. Next, p-type Al 6. ssc ao, +
sAs window layer 4. 'Si, N4 anti-reflection film 5 is opened at required locations, a p-type electrode 6 and a welding pad 8 are formed, and finally an n-type electrode is formed on the back surface of the substrate.
次にそのセル同士の接続方法について説明する。Next, a method of connecting the cells will be explained.
一方の太陽電池のp型GaAs層3上に形成された?容
接用パッド8に溶接されたインタコネクタ9はもう一方
の太陽電池のn型電極7に溶接されている。以上の構造
を繰り返し形成することによって太陽電池が複数個接続
されるようになっている。Is it formed on the p-type GaAs layer 3 of one solar cell? The interconnector 9 welded to the connection pad 8 is welded to the n-type electrode 7 of the other solar cell. By repeatedly forming the above structure, a plurality of solar cells can be connected.
従来のシリコン基板上GaAs太陽電池は以上のように
構成されているので、インタコネクタを溶接用パッドに
溶接する際に圧力、歪みによってSi基板上のエピタキ
シャル結晶層中にクラックが発生し、リークの要因とな
ったり、p型GaAS層3とn型CyaAs層2との接
合特性の劣化が起こるなどの問題点があった。Conventional GaAs solar cells on silicon substrates are constructed as described above, so when the interconnector is welded to the welding pad, cracks occur in the epitaxial crystal layer on the Si substrate due to pressure and strain, resulting in leakage. There have been problems such as deterioration of the bonding characteristics between the p-type GaAS layer 3 and the n-type CyaAs layer 2.
この発明は、上記のような従来のものの問題点を解消す
るためになされたもので、複数個の太陽電池の接続に際
してもクランクの発生がなく、リークの要因もな(、接
合特性の劣化も生じないシリコン基板上化合物半導体太
陽電池およびその作製方法を得ることを目的とする。This invention was made in order to solve the problems of the conventional ones as described above, and there is no cranking when connecting multiple solar cells, there is no cause of leakage (and there is no deterioration of bonding characteristics). The purpose of the present invention is to obtain a compound semiconductor solar cell on a silicon substrate and a method for manufacturing the same that does not cause the formation of a compound semiconductor solar cell on a silicon substrate.
この発明に係るシリコン基板上化合物半導体太陽電池お
よびその作製方法は、Si基板にあらかじめ形成した順
メサ段差部あるいは平面シリコン基板の表面上に部分的
に第1の絶縁膜を形成し、この部分を溶接用パッド部と
するとともに、エピタキシャル結晶層を選択成長により
形成し、その傾斜側面部または鉛直側面部を絶縁膜で保
護し、第2導電型電極をその上にはわせ、インタコネク
タと第2導電型化合物半導体層のみを導通させるように
したものである。A compound semiconductor solar cell on a silicon substrate and a method for manufacturing the same according to the present invention include forming a first insulating film partially on a forward mesa step formed in advance on a Si substrate or on the surface of a flat silicon substrate; In addition to forming a welding pad part, an epitaxial crystal layer is formed by selective growth, its sloped side part or vertical side part is protected with an insulating film, and a second conductivity type electrode is placed thereon to form an interconnector and a second Only the conductive type compound semiconductor layer is made conductive.
この発明においては、溶接用パッド部をエピタキシャル
結晶層と分離して形成するようにしたので、インタコネ
クタ溶接の際にも該エピタキシャル結晶層に圧力、歪み
がかかることはなく、このためクランクの発生はなく、
リークの要因もなく接合特性の劣化も起こらない。In this invention, since the welding pad portion is formed separately from the epitaxial crystal layer, no pressure or strain is applied to the epitaxial crystal layer during interconnect welding, and therefore cranking does not occur. Not,
There is no leakage factor and no deterioration of bonding characteristics.
〔実施例]
以下、この発明の一実施例を図について説明する。第1
図は本発明の一実施例方法により作製されたシリコン基
板上化合物半導体太陽電池を示し、図において、1はS
i基板、2はn型GaAsJli、3はp型GaAs層
、4はp型A I! o、 ss G a o、 t’
sAs窓層、5はSi、N、反射防止膜、6はp型電極
、7はn型電極、8は溶接用パッド、9はインタコネク
タ、10はSiO□膜である。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure shows a compound semiconductor solar cell on a silicon substrate manufactured by the method of one embodiment of the present invention, and in the figure, 1 is S
i substrate, 2 is n-type GaAsJli, 3 is p-type GaAs layer, 4 is p-type AI! o, ss G a o, t'
sAs window layer, 5 is Si, N, antireflection film, 6 is a p-type electrode, 7 is an n-type electrode, 8 is a welding pad, 9 is an interconnector, and 10 is an SiO□ film.
次にその作製方法について説明する。まずSi基板1を
KOH水溶液等で選択エッチし、順メサの段差を形成す
る。次に例えば熱酸化法でSiO□膜10膜設0下部の
みに選択的に形成する。この上にMOCVD法によりn
型GaAs層2.P型GaAs層3.P型A l 6.
lls G a o、 H5A s窓層4を成長する
。この時Sin、膜10上にはエピタキシャル成長は起
こらない。そして、全面にSi2N4反射防止膜5を形
成する。次に穴あけの後、p型電極6.溶接用パッド8
を形成し、基板裏面にn型電極7を形成し、最後にイン
タコネクタ9を溶接する。Next, the manufacturing method will be explained. First, the Si substrate 1 is selectively etched using a KOH aqueous solution or the like to form a mesa step. Next, for example, a thermal oxidation method is used to selectively form the SiO□ film 10 only on the lower part of the film layer 0. On top of this, by MOCVD method, n
type GaAs layer 2. P-type GaAs layer 3. P-type Al 6.
lls Gao, H5A s window layer 4 is grown. At this time, epitaxial growth does not occur on the Sin film 10. Then, a Si2N4 antireflection film 5 is formed on the entire surface. Next, after drilling, p-type electrode 6. Welding pad 8
, an n-type electrode 7 is formed on the back surface of the substrate, and finally an interconnector 9 is welded.
この発明の一実施例によるシリコン基板上GaAs太陽
電池の作製方法においては、Si基板の選択エツチング
は順メサの段差を形成するために必要である。またSi
n、膜10はGaAs選沢成長用として、又、溶接用パ
ッドをn型Siと分離する絶縁体として役立っている。In a method for fabricating a GaAs solar cell on a silicon substrate according to an embodiment of the present invention, selective etching of the Si substrate is necessary to form the steps of the forward mesa. Also, Si
The film 10 serves as a selective growth layer of GaAs and as an insulator to separate the welding pad from the n-type Si.
またSi3N。Also Si3N.
反射防止膜5はn型、n型GaAs層2,3の接合部の
保護膜として、また溶接用パッド8をn型GaAs層2
と分離する絶縁体として役立っている。The anti-reflection film 5 serves as a protective film for the junction between the n-type and n-type GaAs layers 2 and 3, and also serves as a welding pad 8 for the n-type GaAs layer 2.
It serves as an insulator to separate the
また第3図は本発明の他の実施例によるシリコン基板上
化合物半導体太陽電池を示し、図において、第1図と同
一符号は同一の物を示す。Further, FIG. 3 shows a compound semiconductor solar cell on a silicon substrate according to another embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts.
次にその製造方法について説明する。まずSi基板1上
に例えば熱酸化法でSiO□膜10を選択的に形成する
。残りの部分にはMOCVD法によりn型(第1導電型
)GaAs層2. p型(第2導電型)GaAs層3.
P型A l o、 ssG a o、 +sAs窓
層4を成長させる。そして5in2膜lO上および5i
Oz膜10上とエピタキシャル層との界面付近だけを選
択的にエツチング除去することによってSin、膜10
上に付着したポリGaAs粒の除去およびエピタキシャ
ル層の側面の露出(以下、側面出しと称す)を行なう。Next, the manufacturing method will be explained. First, a SiO□ film 10 is selectively formed on a Si substrate 1 by, for example, a thermal oxidation method. The remaining portion is covered with an n-type (first conductivity type) GaAs layer 2. by MOCVD. p-type (second conductivity type) GaAs layer 3.
A P-type A lo, ssG ao, +sAs window layer 4 is grown. and on 5in2 membrane lO and 5i
By selectively etching and removing only the vicinity of the interface between the Oz film 10 and the epitaxial layer, the Sin film 10
The polyGaAs grains attached thereto are removed and the side surfaces of the epitaxial layer are exposed (hereinafter referred to as side exposure).
次に穴あけの後、p型電極6.溶接用パッド8を形成し
、裏面にn型電極7を形成する。最後にインタコネクタ
9を溶接する。Next, after drilling, p-type electrode 6. A welding pad 8 is formed, and an n-type electrode 7 is formed on the back surface. Finally, the interconnector 9 is welded.
本実施例では、5tot膜10はGaAsの選択成長用
として、また溶接パッド8をSi基板と分離する絶縁体
の役目を果たしている。SiO□膜10とエピタキシャ
ル層との界面付近だけをSi基板まで選択的にエツチン
グ除去する工程は良質なn型GaAs層3とn型GaA
s層2との接合部の側面出しをするのに役立っている。In this embodiment, the 5tot film 10 is used for selective growth of GaAs and also serves as an insulator to separate the welding pad 8 from the Si substrate. The process of selectively etching only the vicinity of the interface between the SiO□ film 10 and the epitaxial layer down to the Si substrate is performed using a high-quality n-type GaAs layer 3 and an n-type GaAs layer.
This is useful for exposing the side surface of the joint with the s-layer 2.
S i 3 N4反射防止膜5はまたn型GaAs層3
とn型GaAs層2との接合部の保護膜として溶接パッ
ド8とn型GaAs層2とを分離する絶縁体の役目を果
たしている。The S i 3 N4 antireflection film 5 is also an n-type GaAs layer 3
It serves as a protective film at the junction between the welding pad 8 and the n-type GaAs layer 2, and serves as an insulator to separate the welding pad 8 and the n-type GaAs layer 2.
なお、上記実施例では反射防止膜5にSi、N、、絶縁
膜にSiO□を用いたが、これらはそれぞれTas O
S、Affi、 0.等地の物質であってもかまわない
。In the above embodiment, Si, N, and SiO□ were used for the antireflection film 5, and SiO□ was used for the insulating film, but these were made from Tas
S, Affi, 0. It does not matter if it is a uniform substance.
また、上記実施例ではp−on−n型のSt基板上G
a A s太陽電池について説明したが、これはn−o
n−p型であってもよく、またSt基板上InP太陽電
池等、溶接時のダメージ低減が要求される半導体素子な
ら適用でき、上記実施例と同様の効果を奏する。Furthermore, in the above embodiment, G on the p-on-n type St substrate is
I explained about the aA s solar cell, but this is no
The present invention may be of the n-p type, and can be applied to any semiconductor device that requires damage reduction during welding, such as an InP solar cell on an St substrate, and provides the same effects as the above embodiments.
以上のように、この発明に係るシリコン基板上化合物半
導体太陽電池およびその作製方法によれば、Si基板を
用い、その一部に第1の絶縁膜を、他の部分にエピタキ
シャル結晶層を形成し、また第1および第2導電型化合
物半導体結晶層の接合部分を第2の絶縁膜で保護し、第
1の絶縁膜上に溶接パッドを形成するようにしたので、
インタコネクタ溶接の際にもクランクの発生がなく、接
合特性の劣化も起こらないという効果がある。As described above, according to the compound semiconductor solar cell on a silicon substrate and the method for manufacturing the same according to the present invention, a Si substrate is used, a first insulating film is formed on a part of the silicon substrate, and an epitaxial crystal layer is formed on the other part. Also, since the joint portion of the first and second conductivity type compound semiconductor crystal layers is protected by the second insulating film, and the welding pad is formed on the first insulating film,
There is also no cranking during interconnector welding, and there is no deterioration of bonding characteristics.
第1図はこの発明の一実施例によるシリコン基板上化合
物半導体太陽電池の作製方法を示す断面図、第2図は従
来方法によるシリコン基板上GaAs太陽電池の作製方
法を示す断面図、第3図は本発明の他の実施例によるシ
リコン基板上化合物半導体太陽電池の作製方法を示す断
面図である。
図において、1はSi基板、2はn型GaAs層、3は
p型CaAs層、4はp型A l o、 asG ao
、+sAs窓層、5はSi*N4反射防止膜、6はp型
電極、7はn型電極、8は溶接用パッド、9はインタコ
ネクタ、IOはSin、膜である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view showing a method for manufacturing a compound semiconductor solar cell on a silicon substrate according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing a GaAs solar cell on a silicon substrate by a conventional method, and FIG. FIG. 3 is a cross-sectional view showing a method for manufacturing a compound semiconductor solar cell on a silicon substrate according to another embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is an n-type GaAs layer, 3 is a p-type CaAs layer, 4 is a p-type A lo, asG ao
, +sAs window layer, 5 is a Si*N4 antireflection film, 6 is a p-type electrode, 7 is an n-type electrode, 8 is a welding pad, 9 is an interconnector, and IO is a Sin film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
コン基板の表面上に部分的に形成された第1の絶縁膜と
、 上記第1の絶縁膜を除く上記シリコン基板上に選択成長
により形成された、光電変換を行なう第1及び第2導電
型の化合物半導体結晶層と、該両化合物半導体結晶層の
傾斜側面部または鉛直側面部を被覆するよう設けられた
第2の絶縁膜と、 該第2の絶縁膜上に設けられ他の太陽電池セルとの電気
的接続のためのインタコネクタと上記化合物半導体結晶
層中の第2導電型の化合物半導体層のみを導通させる第
2導電型の電極とを備え、上記第1の絶縁膜上の溶接用
パッド部において上記インタコネクタと上記第2導電型
の電極とを溶接してなることを特徴とするシリコン基板
上化合物半導体太陽電池。(1) A first insulating film partially formed on the lower part of the forward mesa step on the silicon substrate or on the surface of the planar silicon substrate, and a first insulating film formed by selective growth on the silicon substrate excluding the first insulating film. a second insulating film provided to cover first and second conductivity type compound semiconductor crystal layers for photoelectric conversion; and a second insulating film provided to cover inclined side surfaces or vertical side surfaces of both of the compound semiconductor crystal layers; an interconnector provided on the insulating film of No. 2 for electrical connection with other solar cells, and an electrode of a second conductivity type that conducts only the compound semiconductor layer of the second conductivity type in the compound semiconductor crystal layer; A compound semiconductor solar cell on a silicon substrate, characterized in that the interconnector and the second conductivity type electrode are welded to a welding pad portion on the first insulating film.
コン基板の表面上に部分的に第1の絶縁膜を形成する工
程と、 上記第1の絶縁膜上を除いて光電変換を行なう第1及び
第2導電型の化合物半導体結晶層を選択的に成長する工
程と、 上記第1及び第2導電型の化合物半導体結晶層に傾斜側
面部または鉛直側面部を形成する工程と、上記傾斜側面
部または垂直側面部を被覆する第2の絶縁膜を形成する
工程と、 上記第2の絶縁膜上に、他の太陽電池セルとの電気的接
続のためのインタコネクタと上記エピタキシャル結晶化
合物半導体層中の第2導電型の化合物半導体層のみを導
通させる第2導電型の電極を形成する工程と、 上記第1の絶縁膜上に溶接用パッド部を形成する工程と
、 上記溶接用パッド部において上記インタコネクタと上記
第2導電型の電極との溶接を行なう工程とを備えたこと
を特徴とするシリコン基板上化合物半導体太陽電池の作
製方法。(2) forming a first insulating film partially on the lower part of the forward mesa step on the silicon substrate or on the surface of the flat silicon substrate; a step of selectively growing a compound semiconductor crystal layer of a second conductivity type; a step of forming an inclined side surface portion or a vertical side surface portion in the first and second conductivity type compound semiconductor crystal layers; forming a second insulating film covering the vertical side surface; and forming an interconnector for electrical connection with another solar cell on the second insulating film, and forming a second insulating film in the epitaxial crystal compound semiconductor layer. forming a second conductivity type electrode that conducts only the second conductivity type compound semiconductor layer; forming a welding pad portion on the first insulating film; and forming a welding pad portion on the welding pad portion. A method for manufacturing a compound semiconductor solar cell on a silicon substrate, comprising the step of welding a connector and the electrode of the second conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1083278A JPH02260667A (en) | 1989-03-31 | 1989-03-31 | Compound semiconductor solar cell on silicon substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1083278A JPH02260667A (en) | 1989-03-31 | 1989-03-31 | Compound semiconductor solar cell on silicon substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260667A true JPH02260667A (en) | 1990-10-23 |
Family
ID=13797896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1083278A Pending JPH02260667A (en) | 1989-03-31 | 1989-03-31 | Compound semiconductor solar cell on silicon substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260667A (en) |
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| US6281085B1 (en) | 1999-06-28 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
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| US6309939B1 (en) | 1999-06-18 | 2001-10-30 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6365473B1 (en) | 1999-06-29 | 2002-04-02 | Hyundai Electronics Industries Co. Ltd. | Method of manufacturing a transistor in a semiconductor device |
| US6368927B1 (en) | 1999-06-29 | 2002-04-09 | Hyunadi Electronics Industries, Ltd. | Method of manufacturing transistor having elevated source and drain regions |
| US6376318B1 (en) | 1999-06-30 | 2002-04-23 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6406973B1 (en) | 1999-06-29 | 2002-06-18 | Hyundai Electronics Industries Co., Ltd. | Transistor in a semiconductor device and method of manufacturing the same |
| US6478873B1 (en) | 1999-12-30 | 2002-11-12 | Hyundai Electronics Industries Co., Ltd. | Method of optimizing process of selective epitaxial growth |
| US6500719B1 (en) | 1999-12-28 | 2002-12-31 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a MOSFET of an elevated source/drain structure with SEG in facet |
| US6521508B1 (en) | 1999-12-31 | 2003-02-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process |
-
1989
- 1989-03-31 JP JP1083278A patent/JPH02260667A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261911B1 (en) | 1999-02-13 | 2001-07-17 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a junction in a semiconductor device |
| US6277677B1 (en) | 1999-04-12 | 2001-08-21 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6309939B1 (en) | 1999-06-18 | 2001-10-30 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6300209B1 (en) | 1999-06-24 | 2001-10-09 | Hyundai Electronics Industries Co., Ltd. | Method of fabricating triple well of semiconductor device using SEG |
| US6281085B1 (en) | 1999-06-28 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6368927B1 (en) | 1999-06-29 | 2002-04-09 | Hyunadi Electronics Industries, Ltd. | Method of manufacturing transistor having elevated source and drain regions |
| US6365473B1 (en) | 1999-06-29 | 2002-04-02 | Hyundai Electronics Industries Co. Ltd. | Method of manufacturing a transistor in a semiconductor device |
| US6406973B1 (en) | 1999-06-29 | 2002-06-18 | Hyundai Electronics Industries Co., Ltd. | Transistor in a semiconductor device and method of manufacturing the same |
| US6707062B2 (en) | 1999-06-29 | 2004-03-16 | Hyundai Electronics Industries Co., Ltd. | Transistor in a semiconductor device with an elevated channel and a source drain |
| US6376318B1 (en) | 1999-06-30 | 2002-04-23 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device |
| US6500719B1 (en) | 1999-12-28 | 2002-12-31 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a MOSFET of an elevated source/drain structure with SEG in facet |
| US6478873B1 (en) | 1999-12-30 | 2002-11-12 | Hyundai Electronics Industries Co., Ltd. | Method of optimizing process of selective epitaxial growth |
| US6521508B1 (en) | 1999-12-31 | 2003-02-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process |
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