JPH0582829A - Semiconductor light receiving element - Google Patents
Semiconductor light receiving elementInfo
- Publication number
- JPH0582829A JPH0582829A JP3238485A JP23848591A JPH0582829A JP H0582829 A JPH0582829 A JP H0582829A JP 3238485 A JP3238485 A JP 3238485A JP 23848591 A JP23848591 A JP 23848591A JP H0582829 A JPH0582829 A JP H0582829A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- width
- light receiving
- wiring
- side electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体受光素子に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving element.
【０００２】[0002]
【従来の技術】化合物半導体を用いた半導体受光素子は
光通信用素子などに広く用いられている。この光通信用
素子の一例としてＩｎＧａＡｓ ｐｉｎフォトダイオー
ドがあげられる。より大容量の通信のために素子応答特
性の高速化が求められている。応答特性の高速化のため
には素子容量を低減することが重要となる。そのために
は、接合径を充分小さくし、接合容量を低減すると共
に、寄生容量も低減する必要がある。寄生容量を低減す
るための素子構造として、たとえば選択拡散によるｐ+
−ｎ型のプレーナ型素子の場合、半絶縁性基板とメサ構
造による素子分離技術を用いて受光部とは別のメサ分離
された領域にｐ電極を形成し、これとｐ+ 領域とを段差
配線で接続する構造が考えられている。この様な構造を
とることで寄生容量を増やすことなく、素子実装に必要
充分な広い面積を持つｐパッド電極を形成することがで
きる。2. Description of the Related Art A semiconductor light receiving element using a compound semiconductor is widely used as an element for optical communication. An example of this optical communication element is an InGaAs pin photodiode. There is a demand for high-speed device response characteristics for higher capacity communication. It is important to reduce the element capacitance in order to speed up the response characteristics. For that purpose, it is necessary to reduce the junction diameter sufficiently to reduce the junction capacitance and also the parasitic capacitance. As an element structure for reducing the parasitic capacitance, for example, p + by selective diffusion is used .
-In the case of an n-type planar type element, a p-electrode is formed in a mesa-isolated region different from the light-receiving part by using an element isolation technique using a semi-insulating substrate and a mesa structure, and a step is formed between this and the p + region. A structure in which wiring is used for connection is being considered. By adopting such a structure, it is possible to form a p-pad electrode having a large area necessary for mounting an element without increasing the parasitic capacitance.
【０００３】[0003]
【発明が解決しようとする課題】選択拡散によるｐ+ −
ｎ型のプレーナ型のＩｎＧａＡｓ ｐｉｎフォトダイオ
ードを考える。半絶縁性基板を用いて受光部とは別のメ
サ領域を設け、この領域にｐパッド電極を形成し、これ
とｐ+ 領域とを段差配線で接続する構造の素子の場合、
この段差配線をリフトオフ工程により歩留りよく形成す
ることが困難であるという問題点があった。その原因と
して次のようなことが考えられる。例えばブロムとメタ
ノールの混合液によるエッチングによりメサを形成した
とき、その断面をみると、メサエッチングした基底部側
面が深くえぐれたような形状になっていることが多い。
この様な形状に対して段差配線をリフトオフで形成する
ためのレジストマスクを通常のＰＲ工程で作製すると
き、レジスト塗布条件は露光，現像時間などの条件出し
が難しく、このえぐれた部分にレジストが残ってしまう
場合がある。このレジスト残りがリフトオフ時に段差配
線の段切れをひきおこし、歩留り低下の原因となる。P + − by selective diffusion
Consider an n-type planar InGaAs pin photodiode. In the case of an element having a structure in which a mesa region different from the light receiving portion is provided using a semi-insulating substrate, a p pad electrode is formed in this region, and this and the p + region are connected by step wiring,
There is a problem that it is difficult to form the step wiring with a high yield by the lift-off process. The possible causes are as follows. For example, when a mesa is formed by etching with a mixed solution of bromine and methanol, the cross section of the mesa often has a shape in which the side surface of the base portion subjected to mesa etching is deeply carved.
When a resist mask for forming a step wiring by lift-off with respect to such a shape is manufactured by an ordinary PR process, it is difficult to set the resist coating conditions such as exposure and development time. It may remain. The residual resist causes step disconnection of the stepped wiring at the time of lift-off, which causes a decrease in yield.
【０００４】本発明の目的は、このような問題点を解決
した半導体受光素子を提供することにある。An object of the present invention is to provide a semiconductor light receiving element that solves such problems.
【０００５】[0005]
【課題を解決するための手段】前述の課題を解決するた
めに本発明が提供する半導体受光素子は、半絶縁性基板
を用いたプレーナ型フォトダイオードで、拡散領域を含
むメサとは別のメサと拡散領域とを段差配線で結ぶ構造
を持つ半導体受光素子において、拡散領域を含むメサ上
以外の全部分、あるいは一部分の段差配線の幅が、拡散
領域を含むメサ上の幅より大きくなっていることを特徴
とする。In order to solve the above-mentioned problems, a semiconductor light receiving element provided by the present invention is a planar type photodiode using a semi-insulating substrate and is a mesa different from a mesa including a diffusion region. In the semiconductor light receiving element having a structure in which the step region and the diffusion region are connected by a step wiring, the width of the step wiring of all or a part except the mesa including the diffusion region is larger than the width of the mesa including the diffusion region. It is characterized by
【０００６】[0006]
【実施例】以下本発明の一実施例について、図面を参照
して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【０００７】図１は本発明の一実施例を示すｐｉｎフォ
トダイオードの断面構造模式図である。図２は図１の素
子を表面から見た図である。本実施例の構造を、その製
造工程とともに説明する。FIG. 1 is a schematic sectional view of a pin photodiode showing an embodiment of the present invention. FIG. 2 is a view of the device of FIG. 1 viewed from the surface. The structure of this embodiment will be described together with its manufacturing process.
【０００８】まず、半絶縁性ＩｎＰ基板１上に気相成長
法により順次ｎ+−ＩｎＰ２，ｎ- −ＩｎＧａＡｓ３，
ｎ−ＩｎＰ層４の結晶を積層する。その後、Ｚｎの選択
熱拡散により直径４０μｍのｐｎ接合をＩｎＧａＡｓ３
中に形成する。次に、選択エッチングにより受光部を含
むメサ６とｐパッド電極用メサ７を形成する。このとき
のエッチングは半絶縁性基板１に達するまで行うことに
より、これらのメサを電気的に分離している。その後、
プラズマＣＶＤにより素子表面に、パッシベイション膜
と表面反射防止膜とを兼ねた窒化シリコン膜８を形成す
る。最後に、ｐ側電極９及びｎ側電極１０を形成する。
ｐ側電極９は、ｐ+ 領域５上のコンタクト電極部とパッ
ド電極部とを段差配線で接続した構造となっている。こ
の段差配線は受光部を含むメサ６上では太さ５μｍと
し、それ以外の部分では１０μｍとしている。太さ５μ
ｍの部分は、窒化シリコン膜８を介してｎ−ＩｎＰ４と
の間に発生する寄生容量を低減するために細くしてい
る。太さ１０μｍの部分はリフトオフ時の段切れを防ぐ
ために太くしている。First, n + -InP2, n -- InGaAs3 are sequentially formed on the semi-insulating InP substrate 1 by vapor phase epitaxy.
The crystals of the n-InP layer 4 are stacked. After that, a pn junction having a diameter of 40 μm is formed by InGaAs3 by selective thermal diffusion of Zn.
Form inside. Next, the mesa 6 including the light receiving portion and the mesa 7 for the p-pad electrode are formed by selective etching. These mesas are electrically separated by performing the etching at this time until reaching the semi-insulating substrate 1. afterwards,
A silicon nitride film 8 that also serves as a passivation film and a surface antireflection film is formed on the device surface by plasma CVD. Finally, the p-side electrode 9 and the n-side electrode 10 are formed.
The p-side electrode 9 has a structure in which the contact electrode portion on the p + region 5 and the pad electrode portion are connected by a step wiring. This step wiring has a thickness of 5 μm on the mesa 6 including the light receiving portion, and has a thickness of 10 μm in other portions. Thickness 5μ
The portion m is thinned in order to reduce the parasitic capacitance generated between the portion m and n-InP4 via the silicon nitride film 8. The portion with a thickness of 10 μm is thickened to prevent disconnection during lift-off.
【０００９】尚、段差配線の構造としては、本実施例で
示したような形状に限らず、受光部を含むメサ６上では
充分細く、メサ基底部分では充分太い形状であれば他の
形状であっても同様の効果が得られる。The structure of the step wiring is not limited to the shape shown in the present embodiment, but may be any other shape as long as it is sufficiently thin on the mesa 6 including the light receiving portion and sufficiently thick at the mesa base portion. Even if there is, the same effect can be obtained.
【００１０】[0010]
【発明の効果】以上説明したように、本発明によれば寄
生容量を増大させることなく、半導体受光素子を歩留り
よく得ることができる。As described above, according to the present invention, a semiconductor light receiving element can be obtained with a high yield without increasing the parasitic capacitance.
【図１】本発明の一実施例を示すｐｉｎフォトダイオー
ドの断面構造模式図である。FIG. 1 is a schematic sectional view of a pin photodiode showing an embodiment of the present invention.
【図２】図１の素子を表面から見た図である。FIG. 2 is a view of the device of FIG. 1 seen from the surface.
１ 半絶縁性ＩｎＰ基板 ２ ｎ+ −ＩｎＰ ３ ｎ- −ＩｎＧａＡｓ ４ ｎ−ＩｎＰ ５ ｐ+ 領域 ６ 受光部を含むメサ ７ ｐパッド電極用メサ ８ 窒化シリコン膜 ９ ｐ側電極 １０ ｎ側電極1 Semi-insulating InP substrate 2 n + -InP 3 n -- InGaAs 4 n -InP 5 p + region 6 Mesa including light receiving part 7 Mesa for p pad electrode 8 Silicon nitride film 9 p-side electrode 10 n-side electrode
Claims (1)
イオードで、拡散領域を含むメサとは別のメサと拡散領
域とを段差配線で結ぶ構造を持つ半導体受光素子におい
て、拡散領域を含むメサ上以外の全部分、あるいは一部
分の段差配線の幅が、拡散領域を含むメサ上の幅より大
きくなっていることを特徴とする半導体受光素子。1. A planar photodiode using a semi-insulating substrate, which is a semiconductor photodetector having a structure in which a mesa different from a mesa including a diffusion region and a diffusion region are connected by a step wiring, and a mesa including the diffusion region. A semiconductor light-receiving element characterized in that the width of the step wiring in all or a part other than above is larger than the width on the mesa including the diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3238485A JPH0582829A (en) | 1991-09-19 | 1991-09-19 | Semiconductor light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3238485A JPH0582829A (en) | 1991-09-19 | 1991-09-19 | Semiconductor light receiving element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582829A true JPH0582829A (en) | 1993-04-02 |
Family
ID=17030948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3238485A Pending JPH0582829A (en) | 1991-09-19 | 1991-09-19 | Semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0582829A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5870958A (en) * | 1997-04-01 | 1999-02-16 | Nec Corporation | Duplex pallet |
| US6501104B2 (en) * | 2000-04-17 | 2002-12-31 | Nec Corporation | High speed semiconductor photodetector |
| US6586718B2 (en) | 2000-05-25 | 2003-07-01 | Matsushita Electric Industrial Co., Ltd. | Photodetector and method for fabricating the same |
| JP2006351799A (en) * | 2005-06-15 | 2006-12-28 | Fuji Xerox Co Ltd | Surface emitting semiconductor element array |
| JP2008085161A (en) * | 2006-09-28 | 2008-04-10 | Fuji Xerox Co Ltd | Surface emitting semiconductor array element, module, light source device, information processing device, optical transmission device, optical spatial transmission device, and optical spatial transmission system |
| JP2011009702A (en) * | 2009-05-28 | 2011-01-13 | Kyocera Corp | Electronic apparatus, image forming apparatus, and image input apparatus |
| JP2012234958A (en) * | 2011-04-28 | 2012-11-29 | Sumitomo Electric Device Innovations Inc | Semiconductor light receiving device |
| US8610170B2 (en) | 2010-01-25 | 2013-12-17 | Irspec Corporation | Compound semiconductor light-receiving element array |
| US11121268B2 (en) | 2019-05-07 | 2021-09-14 | Lumentum Japan, Inc. | Semiconductor light-receiving element and manufacturing method of semiconductor light-receiving element |
-
1991
- 1991-09-19 JP JP3238485A patent/JPH0582829A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5870958A (en) * | 1997-04-01 | 1999-02-16 | Nec Corporation | Duplex pallet |
| US6501104B2 (en) * | 2000-04-17 | 2002-12-31 | Nec Corporation | High speed semiconductor photodetector |
| EP1148559A3 (en) * | 2000-04-17 | 2003-08-06 | NEC Electronics Corporation | High speed semiconductor photodetector and method of fabricating the same |
| US6586718B2 (en) | 2000-05-25 | 2003-07-01 | Matsushita Electric Industrial Co., Ltd. | Photodetector and method for fabricating the same |
| US6740861B2 (en) | 2000-05-25 | 2004-05-25 | Matsushita Electric Industrial Co., Ltd | Photodetector and method having a conductive layer with etch susceptibility different from that of the semiconductor substrate |
| JP2006351799A (en) * | 2005-06-15 | 2006-12-28 | Fuji Xerox Co Ltd | Surface emitting semiconductor element array |
| JP2008085161A (en) * | 2006-09-28 | 2008-04-10 | Fuji Xerox Co Ltd | Surface emitting semiconductor array element, module, light source device, information processing device, optical transmission device, optical spatial transmission device, and optical spatial transmission system |
| JP2011009702A (en) * | 2009-05-28 | 2011-01-13 | Kyocera Corp | Electronic apparatus, image forming apparatus, and image input apparatus |
| US8610170B2 (en) | 2010-01-25 | 2013-12-17 | Irspec Corporation | Compound semiconductor light-receiving element array |
| JP2012234958A (en) * | 2011-04-28 | 2012-11-29 | Sumitomo Electric Device Innovations Inc | Semiconductor light receiving device |
| US9780249B2 (en) | 2011-04-28 | 2017-10-03 | Sumitomo Electric Device Innovations, Inc. | Semiconductor light-receiving device |
| US11121268B2 (en) | 2019-05-07 | 2021-09-14 | Lumentum Japan, Inc. | Semiconductor light-receiving element and manufacturing method of semiconductor light-receiving element |
| US11705528B2 (en) | 2019-05-07 | 2023-07-18 | Lumentum Japan, Inc. | Semiconductor light-receiving element and manufacturing method of semiconductor light-receiving element |
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