JPH0226068Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse period measuring circuit, and more particularly to a multiple pulse period measuring circuit that measures a plurality of pulse signal periods using a microcomputer.

In recent years, with the rapid development of microcomputers, microcomputers are being used in control units of various devices. In this case, devices using microcomputers perform various controls using pulse signals supplied from various sensors as input, and these pulse signals contain various information such as rotational speed depending on their cycle. There are relatively many things that represent this. Therefore, when handling various input pulse signals using a microcomputer, it is necessary to detect the period of the pulse signals.

In this case, in the pulse period measuring circuit commonly used in the past, an independent circuit is used for each input pulse signal to measure the pulse period.

However, in the above configuration, the circuit configuration is complicated, and when handling a large number of input pulse signals, a pulse period measurement circuit that matches the number of input pulse signals is required, making it extremely complicated and expensive. It has the problem of becoming a thing.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multiple pulse period measuring circuit which has a simple configuration and can easily measure pulse periods for a plurality of input pulse signals. Hereinafter, the multiple pulse period measuring circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a multiple pulse period measuring circuit according to the present invention. In the same figure, 1
is a counter unit, and in this case, the first
- Three counters consisting of a third counter are accommodated. This counter unit then receives the mode select signal MS supplied to the input port CS.
Various counter modes can be selected depending on the mode, but in this case, it is used as a normal counter mode. In other words, the first to third counters sequentially count the clock pulse CLK only during the "H" period of the input pulse signals _IN1 to _IN3 supplied to the input ports _G1 to _G3 corresponding to the respective counters. ,
When the input pulse signals IN ₁ to IN ₃ are inverted to "L", the count value is fixed, and the input pulse signals IN 1 to IN ₃ are inverted to "L".
When _IN3 rises to "H" again, it is reset and starts counting. 2a to 2c are input pulse signals IN ₁
~ IN ₃ is a falling differential circuit that inputs each signal and outputs a falling differential signal (trailing edge differential signal), 3 is a NOR gate that receives the output signals of the falling differential circuits 2a to 2c and calculates a logical sum, and 4 is a It is a microcomputer, and internally includes a means for monitoring which circuit among the falling differential circuits 2a to 2c receives an output, which is activated when the interrupter mode is set by the output signal of the NOR gate 3, and a first circuit in the counter unit 1. - means for selecting a counter from among the third counters that counted the input pulse signal corresponding to the output falling differential circuit;
A means for taking in the count value held by the selected counter and a means for calculating the read count value and measuring the period of the input pulse signal are programmed. Then, the falling differentiation circuit 2a~
Input the output signal of 2c to input ports _P10 to _P12 ,
The output signal of NOR gate 3 is input to input port _P13 for interrupt. Note that _P14 is an output port that supplies the mode select signal MS to the input port CS of the counter unit 1, and _P15 and _P16 are the output ports that supply the first to third input ports _A0 and _A1 of the counter unit 1.
Output port that supplies an address signal specifying the counter; _P17 is an input port that takes in the count value of counter unit 1 via data bus DB; _P18 ,
_P19 is an output port that supplies read/write signals to the input ports _B1 and _B2 of the counter unit 1.

In the circuit configured in this way, when the input pulse signals IN ₁ to IN ₃ are supplied, the first to third counters of the counter unit 1 are connected to the input ports G 1 to G ₁ .
“H” of input pulse signals IN ₁ to IN ₃ supplied to G ₃
The clock pulses CLK are sequentially counted during the period. This count value is then locked when the corresponding input pulse signal is inverted to "L".

On the other hand, the falling differentiation circuits 2a to 2c differentiate the falling portions (trailing edges) of the input pulse signals _IN1 to _IN3 and supply outputs to the input ports _P10 to _P12 of the microcomputer 4. When an "H" level output signal is generated from any of the falling differential circuits 2a to 2c, the output of the NOR gate 3 is inverted to "L" and an interrupt signal is sent to the input port _P13 of the microcomputer 4. Supplied. When the microcomputer 4 is supplied with the interrupt signal, it enters the interrupt mode, reads the signals of the input ports _P10 to _P12 , and determines the input port to which the falling differential pulse is supplied. Then, the microcomputer 4 outputs an output port corresponding to the input port to which the falling differential pulse is supplied.
A counter is specified by generating an address signal AS from P ₁₅ and P ₁₆ , and the count value of this specified counter is read and doubled, and the clock pulse is
The corresponding input signal IN ₁ ~ based on the period of CLK
Find and output the period of IN ₃ . That is, every time the input pulse signal falls, the operation of the counter that has been counting the clock pulses CLK since the input signal is stopped, and the counted value is held. On the other hand, the microcomputer 4 determines the input pulse signal in which an interrupt is added at the falling edge of the input pulse signal and a falling differential pulse is generated, and calculates the count value of the counter controlled by this input pulse signal. The period of the input pulse signal is calculated by importing and calculating. By performing such an operation every time the input pulse signal falls, it is possible to measure the period of a plurality of input pulse signals.

Note that in the above embodiment, a counter unit in which a plurality of counters were integrated was used.
It goes without saying that the present invention is not limited to this, and that each counter may be independent.

As explained above, the multiple pulse period measuring circuit according to the present invention has an excellent effect of easily and reliably measuring the pulse periods for a plurality of input pulse signals, although it has a simple configuration.

[Brief explanation of drawings]

The figure is a circuit diagram showing an embodiment of a multiple pulse period measuring circuit according to the present invention. 1... Counter unit, 2a to 2c... Falling differential circuit, 3... Noah gate, 4... Microcomputer.

Claims (1)

[Scope of utility model registration request] A plurality of counters that are reset when an input pulse signal is supplied and count clock pulses during the supply time of the input pulse signal, and hold the counted value when the input pulse signal is interrupted, and a falling differentiation circuit for the input pulse signal. and a gate circuit that receives the output signal of each of the falling differentiation circuits and generates an OR output thereof, and a plurality of input/outputs connected to the plurality of counters, the plurality of falling differentiation circuits, and the gate circuit. and a microcomputer equipped with a port, the microcomputer being started when it enters the interrupter mode by the OR output of the gate circuit, and monitoring which circuit out of the plurality of falling differential circuits has outputted the signal. and means for selecting, from among the plurality of counters, the counter that counted the input pulse signal corresponding to the outputted falling differential circuit, and capturing the counted value held by the selected counter. and means for measuring the period of the input pulse signal by calculating the loaded count value.