JPH02260696A - Method of inspecting multilayer printed board - Google Patents
Method of inspecting multilayer printed boardInfo
- Publication number
- JPH02260696A JPH02260696A JP8288189A JP8288189A JPH02260696A JP H02260696 A JPH02260696 A JP H02260696A JP 8288189 A JP8288189 A JP 8288189A JP 8288189 A JP8288189 A JP 8288189A JP H02260696 A JPH02260696 A JP H02260696A
- Authority
- JP
- Japan
- Prior art keywords
- printed board
- hole
- board
- aligned
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、多層プリント基板の孔加工において孔加工前
に孔加工してもよいかどうかの検査をする方法に係る。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for inspecting whether or not hole processing is permitted before hole processing in a multilayer printed circuit board.
〈従来技術〉
従来は、実測して検査するか、実際に孔をあけてから正
しく了し加工できたか検査していた。<Prior Art> Conventionally, the holes were actually measured and inspected, or holes were actually drilled and then inspected to see if they were completed correctly.
〈発明が解決しようとする課題〉
実測する場合、検査する点が多く、またいろいろ距離を
測って比べるのは手間で面倒だった。<Problem to be solved by the invention> When actually measuring, there are many points to inspect, and it is time-consuming and troublesome to measure and compare various distances.
また孔をあけてしまった場合、修正は困難である。また
、その加工だけ工程ロスとなり、また、材料ロスの原因
ともなる。Furthermore, if a hole is made, it is difficult to repair it. In addition, the processing alone causes process loss and also causes material loss.
従って、孔加工が行なわれる前に簡単に検査できる多層
プリント基板の検査方法が求められていた。Therefore, there has been a need for a method for inspecting multilayer printed circuit boards that can be easily inspected before holes are formed.
〈課題を解決するための手段〉
上述の方法を、特許請求の範囲に示し技術で解決しよう
とするものである。<Means for Solving the Problem> The above-mentioned method is attempted to be solved by the technology shown in the claims.
く作用〉
テストボートは、本来ドリル孔形成後ドリル孔位置確認
の為やドリル孔の数チエツク用や基板伸縮状況チエツク
用、焼付フィルム(実用版)焼付用基準孔明は治具作成
用等に使用している伸縮の殆どない孔だけが形成されて
いる金属またはべ一りなどの樹脂の板の事で、これを用
いるとテストボードによりX線が遮蔽される孔部と他の
部分との境界が明確になり、正しく孔がおいているかど
うかを一目瞭然と判別する事が出来る。Function〉 The test boat is originally used to confirm the position of the drill hole after forming the drill hole, to check the number of drill holes, to check the expansion and contraction status of the board, and the reference holes for baking the baking film (practical version) are used for making jigs, etc. A board made of metal or resin, such as a plate, that has only holes with almost no expansion or contraction, and when used, the boundary between the hole and other parts where X-rays are shielded by the test board. becomes clear, making it possible to determine at a glance whether or not the holes are placed correctly.
〈実施例〉
第1図は、本発明の一実施例を示す側面断面図であり、
第2図は同X線平面視図である。<Example> FIG. 1 is a side sectional view showing an example of the present invention,
FIG. 2 is an X-ray plan view of the same.
多層プリント基板は銅の多層配Li1.235.6間に
はガラエボの絶縁層7が形成されている。そのある配線
1,4.6とは接触しまた層2゜3.5とは接触しない
様に孔をあけないと信号ライン不良となる状態となって
いる。ここでテストボード8を上から位置合せした上で
X線で透視すると、仮想ドリル孔位置20にドリル孔を
あけても良いかどうかが一目瞭然となる。つまり、配線
の輪郭11.12.13.14.15.16とテストボ
ートの孔18との関係で層間ずれが発生している孔をあ
ける余地がなかったり、多層プリント基板に伸縮が発生
して孔をあけて不良となることが判る。In the multilayer printed circuit board, an insulating layer 7 of Galevo is formed between the copper multilayer wiring Li1.235.6. If holes are not made so that the holes are in contact with the wirings 1, 4.6 and not in contact with the layer 2.3.5, the signal line will be defective. Here, when the test board 8 is aligned from above and viewed through X-ray, it becomes clear at a glance whether or not a drill hole can be drilled at the virtual drill hole position 20. In other words, due to the relationship between the wiring outline 11, 12, 13, 14, 15, 16 and the hole 18 of the test boat, there may not be enough room to drill a hole where layer misalignment has occurred, or there may be expansion and contraction in the multilayer printed circuit board. It can be seen that the hole becomes defective.
〈発明の効果〉
本発明により、ドリル孔加工前に良不良のチエツクが出
来、孔あけ位置をずらしたりピンチを変えたりして微調
整して不良としない様にする事が出来る。<Effects of the Invention> According to the present invention, it is possible to check whether the hole is good or bad before drilling a hole, and it is possible to make fine adjustments by shifting the drilling position or changing the pinch to prevent defects.
また、工程不良をすぐ前の工程に情報をフィードドック
する事が出来る。In addition, it is possible to feed information about process defects to the immediately previous process.
第1図は、本発明の一実施例を示す側面断面図であり、
第2図は同X線平面視図である。
1.2,3,4,5.6・・・配線
7・・・・・・絶縁層
8・・・・・・テストボード
11、12.13.14.15.16・・・配線の輪郭
18・・・・・・テストボードの孔
20・・・・・・仮想ドリル孔位置
時 許 出 願 人
凸版印刷株式会社
代表者 鈴木和夫FIG. 1 is a side sectional view showing one embodiment of the present invention,
FIG. 2 is an X-ray plan view of the same. 1.2, 3, 4, 5.6... Wiring 7... Insulating layer 8... Test board 11, 12.13.14.15.16... Outline of wiring 18...Test board hole 20...Virtual drill hole position Applicant Kazuo Suzuki, Representative of Toppan Printing Co., Ltd.
Claims (1)
、X線で透視する事によりドリル孔加工余地があるかど
うか判定する多層プリント基板の検査方法。1) A multilayer printed circuit board inspection method in which a test board is aligned on the printed circuit board and examined with X-rays to determine whether there is room for drilling holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082881A JP2754695B2 (en) | 1989-03-31 | 1989-03-31 | Inspection method of multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082881A JP2754695B2 (en) | 1989-03-31 | 1989-03-31 | Inspection method of multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02260696A true JPH02260696A (en) | 1990-10-23 |
| JP2754695B2 JP2754695B2 (en) | 1998-05-20 |
Family
ID=13786618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1082881A Expired - Fee Related JP2754695B2 (en) | 1989-03-31 | 1989-03-31 | Inspection method of multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2754695B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139706A3 (en) * | 2000-03-28 | 2003-07-02 | Adtec Engineering Co., Ltd. | Positioning apparatus used in a process for producing multi-layered printed circuit board and method of using the same |
| CN110876240A (en) * | 2018-09-04 | 2020-03-10 | 胜宏科技(惠州)股份有限公司 | Method for detecting drilling deviation of multilayer circuit board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58140196A (en) * | 1982-02-15 | 1983-08-19 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS624503A (en) * | 1985-06-28 | 1987-01-10 | Mitsubishi Electric Corp | Manufacture of multi-layered printed wiring board |
| JPS63136812A (en) * | 1986-11-28 | 1988-06-09 | Nec Corp | Pulse generating device |
-
1989
- 1989-03-31 JP JP1082881A patent/JP2754695B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58140196A (en) * | 1982-02-15 | 1983-08-19 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS624503A (en) * | 1985-06-28 | 1987-01-10 | Mitsubishi Electric Corp | Manufacture of multi-layered printed wiring board |
| JPS63136812A (en) * | 1986-11-28 | 1988-06-09 | Nec Corp | Pulse generating device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139706A3 (en) * | 2000-03-28 | 2003-07-02 | Adtec Engineering Co., Ltd. | Positioning apparatus used in a process for producing multi-layered printed circuit board and method of using the same |
| CN110876240A (en) * | 2018-09-04 | 2020-03-10 | 胜宏科技(惠州)股份有限公司 | Method for detecting drilling deviation of multilayer circuit board |
| CN110876240B (en) * | 2018-09-04 | 2021-07-02 | 胜宏科技(惠州)股份有限公司 | Method for detecting drilling deviation of multilayer circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2754695B2 (en) | 1998-05-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |