JPH02260772A - Interpolation circuit for digital signal - Google Patents

Abstract

PURPOSE:To improve output frequency characteristics by using a rapid clock whose frequency is higher than that of an original sampling clock to be used for writing a video signal stored in a frame memory to read out the video signal and executing linear interpolation by the video signal. CONSTITUTION:A rapid interpolation circuit 25 finds out the product of digital data 31 and an interpolation coefficiency k1 and the product of digital data 32 and an interpolation coefficiency (1-k1) and adds these products to each other. In addition, the circuit 25 finds out the product of digital data 33 and the coefficiency k1 and the product of digital data 34 and the coefficiency (1-k1) and adds these products to each other. In order to consider a vertical interpolation value, these two added results are respectively multiplied by an interpolation coefficiency k2 or (1-k2) and adds these multiplied results. The data 36 of an interpolation point are supplied to a D/A converter 37 and covered into an analog image signal 38 at the supply timing of a sampling clock 17 and the signal 38 is supplied to a video signal output terminal 39. Consequently, the deterioration of the frequency characteristics which may be generated in the interpolation circuit can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal interpolation circuit used in a digital special effects device that performs signal processing such as enlarging or reducing a television signal.

[Conventional technology]

Broadcasting stations and the like use digital special effects devices to perform signal processing such as enlarging and reducing television signals. When enlarging a television signal, it is necessary to obtain data at a new point based on sampled data at a known point. For this purpose, an interpolation circuit is used that obtains data at new points by linear interpolation on the premise that data changes linearly between known points.

FIG. 3 shows a conventionally used digital signal interpolation circuit.

This circuit is provided with two input terminals: a reference signal input terminal 11 and a video signal input terminal 12. For example, a horizontal synchronizing signal is manually inputted as a reference signal 13 from the input terminal 11 . This reference input signal 13 is input to the PLL circuit 51. The PLL circuit 51 generates a clock 52 at the original sampling frequency of the video signal based on this reference input signal 13. This clock 52 is connected to an A/D converter 53, a frame memory 54, and an interpolation circuit 5.
5, a D/A converter 56, a write address generator 57, and a read address generator 58, respectively.

Here, the video signal 10 to be enlarged or reduced is inputted to the A/D converter 53 from the input terminal 12, and is sequentially sampled by the sampling clock 52 and A/D converted. . The digital video signal 61 output from the A/D converter 53 is supplied to the frame memory 54 and written in the input order by the clock 52.

FIG. 4 shows an example of an image written to this frame memory. Each scanning line is stored in the frame memory 54! Data at each original sampling point such as a, b, c, and d sampled at each sampling point S by the clock 52 is inputted every time. In this FIG. 4, a rectangular part 60 is the subject of a certain video, and each of the four representative sampling points a and b
.

c and d are points selected to find the point P that is currently necessary surrounded by these by interpolation.

By the way, the read address generator 58 in FIG.
A shape conversion operation is performed on the write address to generate a read address 62. This read address 62 is supplied to the frame memory 54.

Further, the read address generator 58 supplies two interpolation coefficients, , k, to the interpolation circuit 55, which are determined from the positional relationship between the sampled video signal and the point to be linearly interpolated. These interpolation coefficients, k2, are obtained as the decimal part of the calculation result of the read address generator 24.

The frame memory 54 reads out the four original sampling points that two-dimensionally surround the data after the shape conversion at a read address 62.
read out simultaneously using These digital data6
4 to 67 are sent to the interpolation circuit 55. The interpolation circuit 55 uses two original sampling points in the same horizontal direction to obtain the interpolation amount in that direction. Find the product of the coefficients N- and +) and add them.

Also, in order to obtain the interpolation amount in that direction using the two original sampling points for the next scanning line, the product of the digital data 66 and the interpolation coefficient and the digital data 6
7 and the interpolation coefficient N- (+), and add these. Then, in order to consider the amount of interpolation in the vertical direction for these two addition results, the interpolation coefficients are each multiplied by 2 or (1-2), and then these are added.

FIG. 5 shows an example of video data read out from the frame memory, and corresponds to FIG. 4 as a video input. Data regarding point P is required on the new scan line β', and this data is for each of the four original sampling points a and b mentioned above.

It can be found from c and d. Assuming that point P is located exactly in the middle of each original sampling point a, b, c, d, the interpolation coefficients k and k2 mentioned above are both 0.5.
Therefore, the calculation formula for point P is the following formula (1).

When the interpolation circuit 55 performs the sum-of-products operation in this way,
The resulting interpolation point data 68 is sent to the D/A converter 5.
6. In the D/A converter 56, the clock 52
The interpolation point data 68 is converted into an analog signal 69 at the timing when the signal is supplied, and the analog signal 69 is supplied to the video signal output terminal 39.

[Problems to be Solved by the Invention] FIG. 6 shows the output frequency characteristics when this conventional digital signal interpolation circuit is used. FIG. 6 shows the case where the point to be interpolated is exactly in the middle of the two referenced original sampling points, that is, the case where the worst characteristic is exhibited. In the figure, the vertical axis represents the amplitude level, and the horizontal axis represents the frequency.

In this conventional circuit, if the original sampling frequency by the clock 52 is f, the frequency characteristic after linear interpolation is represented by a cosine characteristic 71. In this way, the quality deteriorates due to the characteristic of zero crossing at the frequency 1/2"S, which is 1/2 of the sampling frequency, so it is difficult to obtain a high-quality image when displaying an image using point data obtained by interpolation. It was difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal interpolation circuit that can improve the deterioration of shift characteristics caused by linear interpolation.

[Means to solve the problem]

In the present invention, (i) an original sampling clock generating means for generating an original sampling clock for sampling a video input signal; (ii) a frame memory for storing a video input signal sampled using the original sampling clock; 111) high-speed clock generation means for generating a high-speed clock having a higher frequency than the original sampling clock; and (iv) video signal reading means for simultaneously reading out video signals at multiple points used for interpolation from the frame memory using the high-speed clock. , (v) interpolation calculation means for calculating a video signal at a desired point by performing linear interpolation using the video signals at the plurality of points, and (vi) original sampling of the video signal after calculation by the interpolation calculation means. A digital signal interpolation circuit is provided with sampling means for sampling with a clock and producing a video output signal.

By processing the video signal stored in the frame memory with a clock having a higher frequency than the original sampling clock, the zero-crossing point in the cosine characteristic is shifted to the higher frequency side, thereby reducing the deterioration of the characteristic in the used frequency band.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows a digital signal interpolation circuit in one embodiment of the present invention.

This circuit is provided with two input terminals: a reference signal input terminal 11 and a video signal input terminal 12. For example, a horizontal synchronizing signal is manually inputted as a reference signal 13 from the input terminal 11 . This reference input signal 13 is input to a PLL circuit 14. Based on this reference input signal 13, the PLL circuit 14 generates a clock 15 having a frequency twice the original sampling frequency of the video signal. This clock 15 is input to a 1/2 multiplier 16,
A sampling clock 17 with a frequency of 2 is created.

This sampling clock 17 is connected to an A/D converter 18, a high-speed frame memory 19, and a write address generator 2.
Sent to 1.

Here, a video signal 1o to be enlarged or reduced is input to the A/D converter 18 from the input terminal 12, and is sequentially sampled by the sampling clock 17 and A/D converted. The digital video signal 22 output from the A/D converter 18 is supplied to the high-speed frame memory 19, and written in the order of input by the sampling clock 17 input to its writing system.

By the way, a clock 15 with a frequency twice the original sampling frequency output from the PLL circuit 14 is sent to a high-speed frame memory 19, a read address generator 24, and a high-speed interpolation circuit 25, and the digital video from the high-speed frame memory 19 is It is used to read out the signal 22. Here, the read address generator 24 generates twice the address data by linearly interpolating the write address. This address data is subjected to a shape conversion operation, and the read address 27 obtained as a result is sent to the high speed frame memory 19. Further, the read address generator 24 supplies two interpolation coefficients, , and , which are determined from the positional relationship between the sampled video signal and the point to be linearly interpolated, to the high-speed interpolation circuit 25 . These interpolation coefficients + and 2 are
It is obtained as the decimal part of the calculation result of the read address generator 24.

The high-speed frame memory 19 stores the data after shape conversion.
Four dimensionally surrounding original sampling points are simultaneously read out using read addresses 27. These digital data 31 to 34 are sent to a high speed interpolation circuit 25. The high-speed interpolation circuit 25 uses two original sampling points in the same horizontal direction to obtain the interpolation amount in that direction. Find the product of the coefficients (1- to +) and add them. In addition, in order to obtain the interpolation amount in that direction using the two original sampling points for the next scanning line, we multiply the digital data 33 and the interpolation coefficient by 1, and the digital data 34 and the interpolation coefficient (1 Find the product of −, ) and add these.

Then, in order to consider the amount of interpolation in the vertical direction for these two addition results, the interpolation coefficients are set to 2 or (1).
-1) and then add these together.

When the high-speed interpolation circuit 25 performs the sum-of-products operation in this way, data 36 at the interpolation point as a result is supplied to the D/A converter 37. The D/A converter 37 converts the data 36 at the interpolation point into an analog image signal 38 at the timing when the sampling clock 17 is supplied, and supplies it to the output terminal 39 of the video signal.

FIG. 2 corresponds to FIG. 6 and shows the output frequency characteristics when the digital signal interpolation circuit of this embodiment is used. FIG. 2 shows the case where the point to be interpolated is exactly in the middle of the two referenced original sampling points, that is, the case where the worst characteristic is exhibited. In the figure, the vertical axis represents the amplitude level, and the horizontal axis represents the frequency. In the circuit of this embodiment, the PLL circuit 14
is used to convert the sampling frequency to the original sampling frequency f
The frequency is set to 2fs, which is twice that of . Therefore, the zero crossing point of the cosine characteristic 41 has moved from the conventional t/2fs to f. As a result, deterioration in frequency characteristics caused by this interpolation circuit can be significantly reduced.

Note that in the embodiment, the degree of oversampling was doubled, but if the degree of oversampling is more than 1, the conventional frequency t/2f
The zero crossing point at s can be moved to the higher frequency side, and deterioration of frequency characteristics can be reduced. The degree of this deterioration decreases as the sampling frequency increases, but the degree of improvement resulting from this is not necessarily commensurately significant. Furthermore, as the sampling frequency increases, it becomes more difficult to configure the high-speed frame memory 19 and the high-speed interpolation circuit 25 that respond to the clock 15. Therefore, when implementing the present invention, it is necessary to determine the sampling frequency based on both the degree of improvement in characteristics and the circuit configuration.

〔Effect of the invention〕

As explained above, according to the present invention, a high-speed clock having a higher frequency than the original sampling clock used for writing the video signal stored in the frame memory is used to read out the video signal. Since linear interpolation is performed using the video signal, the zero-crossing point in the cosine characteristic can be shifted to the high frequency side, and the output frequency characteristic can be easily improved.

[Brief explanation of drawings]

Figures 1 and 2 are for explaining one embodiment of the present invention. Figure 1 is a block diagram of a digital signal interpolation circuit, and Figure 2 shows the frequency characteristics using this circuit. 3 is a block diagram of a conventionally used digital signal interpolation circuit, and FIG. 4 is an explanatory diagram showing an example of the contents of a video signal input to the frame memory of this circuit.
FIG. 5 is an explanatory diagram showing an example of the contents of a video signal output from the frame memory, and FIG. 6 is a characteristic diagram showing frequency characteristics using a conventional circuit. 10...Video signal, 13...Reference signal, 14...PLL circuit, 16...1/2 multiplier, 18...・A/D converter, 19...High-speed frame memory, 24...
- Read address generator, 25... High-speed interpolation circuit, 37... D/A converter, 38... Analog image signal. 2 figures, 4 figures, 5 circles, 6 figures

Claims (1)

[Scope of Claims] Original sampling clock generation means for generating an original sampling clock for sampling a video input signal; a frame memory for storing a video input signal sampled using the original sampling clock; a high-speed clock generating means for generating a high-speed clock with a high frequency; a video signal reading means for simultaneously reading video signals at a plurality of points used for interpolation from the frame memory using the high-speed clock; interpolation calculation means for calculating a video signal at a desired point by performing linear interpolation using the interpolation calculation means; and sampling means for sampling the video signal after the calculation of the interpolation calculation means using the original sampling clock to obtain a video output signal. A digital signal interpolation circuit comprising: