JPH02260942A - Digital exchange - Google Patents

Abstract

PURPOSE:To improve the data exchange efficiency of a digital exchange by transmitting and receiving data at every period corresponding to the number of frequencies decided by means of a deviation between a reference data transmitting quantity and the data transmitting quantity of terminal equipments as to the terminal equipments whose data transmitting quantity is less than the reference data transmitting quantity. CONSTITUTION:When the data transmitting quantity of the terminal equipments A and B is 1/2 of the reference data transmitting quantity, the terminal equipment A is designated at every other frame, for example, and data of the terminal equipment A is exchanged in the time slots t3 of frames F1 and F3. In the time slots t3 of frames F2 and F4, the terminal equipment B is designated and data is exchanged. Thus, the digital exchange 11 can effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital exchange that is suitably applied to a telephone exchange to which a plurality of terminal devices such as telephones are connected.

Conventional technology FIG.
520 is a circuit diagram showing the configuration of the time switch circuit 2 in the digital exchange 1. FIG. A plurality of terminal devices T1 to Trr are connected to the digital exchange 1 via a line 11. As shown in FIG. 3 (2), the digital exchange 1 divides a certain period of time, for example, a period called a frame of 125 μsec, by the terminal device Rn with which data is to be exchanged, and
Each terminal device T1 to Tn is sequentially designated for each divided period called a slot to transmit and receive data 1M.

Data is sent and received once every 125 μsec, that is, once every 125 μsec.
Since the data transmission is performed in units of 8 bits 5ooo times per second, the data transmission amount is 64 kbit/sec. A synchronizing signal is applied to the terminal devices T1 to Tn via a line 12, and address data from a counter 5, which will be described later, is applied via a line 13. Based on these synchronization signals and address data, the terminal devices T1 to Tn are sequentially designated for each time slot, and only the designated terminal devices can perform digital communication J! ! Sends and receives data to and from 11.

The time switch circuit 2 includes a time slot memory 3, changeover switches 4 and 6, a counter 5, and a connection memory 7.
and a control section 8. Terminal device T1-T
Transmission and reception of data to and from rr is performed via time slot (2) and memory 3. When data is input, the count value of the counter 5 is given to the time slot memory 3 as write address data. The count value of counter 5 increases by 1 from 1 to rl every time slot, so
In time slot memory 3, addresses #1 to #
The r crows are sequentially designated, and the data of the terminal devices rltTl to Tn are sequentially stored in the storage areas to which these addresses are assigned.

When outputting data, turn off the selector switch 4 if A
By doing so, the data of connection memory 1 NOA is given to the time slot memory go as read address data. Connection memory 7! The output address data given from the 11th section 8 is stored. The count value of the counter 5 is given to the connection memory 7 via the switch notch 6. 2hL hence connection memory 7
In , addresses #1 to #n are specified sequentially,
These read address data stored in the storage areas to which responses are assigned are sequentially applied to the memory 3 in the tile 1 and the slot 7). The time slot memory 3 provides the data stored at the address designated by the connection memory 7 to each terminal device via a line 11.

To explain in detail with reference to FIG. 3 <2>, data from the terminal device T1 is first given to the time slot memory 3 in the time slot t1. At this time, the output of the counter 5 is "1", and by giving the output of the counter 5 to the time slot memory 3, the terminal device WT1
The data is at address #1 of time slot memory 3.
By switching the changeover switch 4.6, the output of the counter 5 is applied to the connection memory 7 via the changeover switch 6.

As a result, the connection memory 7 provides the data stored in the storage area at address #1, for example 4f "2", to the time slot memory 3. - As a result, the time slot memory 3 gives the data stored at address #2 to the terminal device T1.

In this manner, data is transmitted and received between the digital exchange 1 and the terminal WTI.

Problems to be Solved by the Invention The standard data transmission amount of the above-mentioned digital exchange FIT is 64
k bit / sec, but even in the case of a terminal device whose data transmission amount is smaller than the standard data transmission amount, the terminal device is assigned to one time slot and data transmission and reception with the digital exchange 1 is not possible. It is being done.

Therefore, the data transmission amount is, for example, 32 kb i
In the case of a T/sec terminal device, data transmission and reception in one time slot is in units of 4 bits,
There is a problem that the data exchange efficiency of the digital exchange 1 becomes low.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a digital exchange that improves the efficiency of data exchange.

Means for Solving the Problems The present invention provides a digital exchange to which a plurality of terminal devices are connected and which periodically and sequentially designates the terminal devices and transmits and receives data for each predetermined data capacity. An identification device that periodically outputs identification data that identifies the cycle within each institution corresponding to a frequency determined in accordance with the deviation between the standard data transmission amount determined by the standard data transmission amount and the data transmission amount of the terminal device. data output means, and address data output means for repeatedly outputting predetermined class A address data every cycle; This digital exchange is characterized in that a terminal device is specified for each institution using address data.

For production According to the present invention, a plurality of terminal devices are connected.

In a digital exchange that periodically and sequentially designates terminal devices to transmit and receive data for each predetermined data capacity, the terminal device whose data transmission amount is the standard data transmission amount is
It is designated by a predetermined type of address data output from the address data output means every cycle, and data transmission and reception is performed every cycle.

A terminal device whose data transmission amount is less than the standard data transmission amount sends and receives data to and from each engine corresponding to a frequency determined by the deviation between the standard data transmission amount and the data transmission amount of the terminal device. That is, a specific cycle within the engine is designated by the identification data from the identification data output means, and within that cycle, a terminal device is designated by the address data from the address data output means, and data is transmitted and received. Therefore, data can be sent and received by specifying a terminal device with the same deviation in other cycles within the engine. With this, digital sentence IA
The efficiency of machine data exchange is improved.

Embodiment FIG. 1 shows a digital exchange 11 which is a first embodiment of the present invention.
It is a circuit diagram showing the configuration of the time switch circuit 12 of
2I2I is a diagram showing the connection relationship between the digital exchange 1c1 machine 11 and the terminal device, and FIGS. 312 and 4 are diagrams for explaining the basic schedule of data exchange in the digital exchange 8111. A plurality of terminal devices are connected to the digital text 10 machine 11 via a line 15. As shown in No. 311Z(2), the digital exchange 11 divides a certain period of time, for example, a period called a frame of 125 μsec, by the number n of terminal devices to exchange data, and divides it into divisions called time slots. Data exchange is performed by sequentially specifying terminal devices for each institution.

Data exchange is performed in units of 8 bits once every 125 μsec, that is, 8000 times per second, so the standard data transmission amount is 64 kbit/sec. The terminal device includes the output of the multi-frame counter 13, a synchronization signal,
Address data from the time slot counter 20 are provided via lines l6.17.18, respectively.

The digital exchange 11 includes a time switch circuit 12 and a multi-frame counter 13 serving as identification data output means, and the time switch circuit 12 includes a time slot memory 14 . Off fA switch 15, 16. It is configured to include a connection memory 17, a control section 18, an arithmetic circuit 19, and a time slot counter 2o which is address data output means.

Data exchange between the digital communication Afill and the terminal device can be realized using the time slot memory 14 realized by random access memory (RAM) or the like. Address and time slot memory 1
It is necessary to set an address for reading data from 4 in synchronization with each time slot t-ti to tn. The address when writing data is from time slot t1.
Since it is sufficient to sequentially give n from 1 to n in synchronization with t rI, addresses 1tl11 at the time of writing can be easily realized by using the time slot counter 20 which increments by 1 for each time slot.

On the other hand, the order of addresses at the time of reading is time slot t
Since there is no correlation with the R number from 1 to trr and there is no regularity, it is necessary to have a correspondence table of read addresses corresponding to tie 11 slots t1 to tn. Since it is necessary to be able to exchange data with any terminal device, this compatible J2 is equipped with a random access memory (RA).
A conexisin memory 17 realized by M) or the like is used, and the read address can be arbitrarily set.

The conexigine memory 17 stores time slots t1 to t.
Addresses at which data should be read from the time slot memory 14 in time slots 1 to tn are written to addresses corresponding to n, that is, addresses #1 to #n, respectively. As shown in No. 4121, when reading time slot t1, time slot memory read address data "2" is read from address #1 of connection memory 17, and this address data "2" causes address #2 of time slot memory 14 to be read. The data DB is read from. Furthermore, when reading the next time slot)-t2, the read address data "1" of the time slot memory 14 is read from the address #2 of the connection memory 17, and this address data "1" causes the read address data "1" of the time slot memory 14 to be read from address #2 of the connection memory 17. Data DA is read from 1. Thereafter, ijl is sequentially applied up to time slot tn.
tI, and then again at time slot t1 of the next cycle.
Repeat the control from.

On the other hand, since the address control of the connection memory 17 can be assigned to addresses #1 to #n in synchronization with the time slots t1 to tn, the time slot counter for controlling the write address of the time slot memory 14 (i.e. 2o can be shared, and can be realized in the same manner as the write 1t11 control of the time slot memory 14. Also, writing of the read address of the time slot memory 14 to the connection memory 17 is performed by the control unit 1.
8.

In this manner, the digital exchange 11 can designate a terminal device for each time slot in one frame period and perform data exchange. Here, the data transmission amount of terminal devices A and B is 1/2 of the standard data transmission amount, that is, 32 kbit/
Assume that sec. Such a terminal bag mA,
Even if B specifies, for example, terminal device A for each time slot in one frame period, the data exchange in one time slot will be in units of 4 bits.

For example, if you specify the terminal bag fiA every other frame,
Data exchange can be performed in units of 8 bits, but in this case there will be unused time slots every other frame. In other words, as shown in No. 311<2), in time slot t3 of frames Fl and F3, data exchange of terminal bag ZA is performed, but frame F
2. Time slot t3 of F4 will not be used.

Therefore, this frame F2. F, 4 time slot)+
In step 3, if the terminal device B is designated for data exchange, the digital exchange 11 can be used effectively. Such a data exchange method is called r2 multiframe method 2.

In order to realize such a two-multiframe system, the terminal bag ZA,n contains the output from the multiframe counter 13 in addition to the address data given from the time slot counter 20 to specify the time slot. A signal SL with a period of 250 μsec is applied. As a result, when the signal Sl is at a low level, that is, "0", and the address data is "r3", that is, frame F1. At time slot t3 of F3, the terminal bag HA transmits and receives data, and the second signal S1 is at a high level, that is, "
I, when the address data is "3", that is, frame F2. At time slot t3 of F4, terminal bag RB
sends and receives data.

Further, in the time switch circuit 12, for example, 8-bit data from the time slot counter 20,
For example, 2-bit data from the multi-frame counter 13 is calculated by the calculation circuit 19 to become address data in units of 10 bits, and the address data is stored in the time slot memory 1.
4 and connection memory 17, respectively. As a result, the address specified in the time slot t3 becomes a different address depending on the output of the multi-frame counter 13, and the data exchange of the terminal bags WA, +3 can be performed independently. Also, the data transmission amount is 1/rn of the standard data transmission amount (m = 3.4...)
The same implementation can be applied to the terminal device.

As described above, according to this embodiment, the digital exchange 11 can be used effectively even when exchanging data between terminal devices whose data transmission amount is less than the standard data transmission amount.
Further, data exchange can be performed by mixing terminal devices with different data transmission amounts, and the efficiency of data exchange of the digital exchange 11 is improved.

FIG. 5 is a block diagram for explaining the second embodiment of the present invention, and 611J is a timing chart for explaining its operation.1 This embodiment is similar to the first embodiment described above. Therefore, the same reference numerals are used for the same configuration (-f
In this embodiment, the data transmission amount is 1/4 of the standard data transmission amount, that is, 16 kbit/s.
Terminal devices A and B are e c.

A so-called 4 multi-frame system has been realized in which C and D data are exchanged.

The terminal devices A, B, C, and D are given a signal S1 with a period of 250 μsec and a signal S2 with a period of 500 μsec. These signals SL and S2 can represent four states as multi-frame information. Therefore, with reference to No. 6 [2I, signal 31. In frame F1, where S2 is both low level, data exchange is performed by terminal device A, and in frame F2, where signal S1 is high level and signal S2 is low level, data exchange is performed by terminal device B. Furthermore, in frame F3 where the signal S1 is at a low level and signal S2 is at a high level, data is exchanged by the terminal device C, and in frame F4 where both signals SL and S2 are at a high level, data is exchanged by the terminal device rIID. The same effects as in the first embodiment described above can be obtained in the six embodiments.

7I2I is a block diagram for explaining the third embodiment of the present invention. This embodiment is similar to the above-described embodiment 1'A, so the same reference numerals are used for the same components. Attached 0
In this embodiment, a 2-multiframe system is realized.The feature of this embodiment is that the multi-frame pulse generation circuit 21 is used as a 4-separate data output means.

The multi-frame pulse generating circuit 21 generates a signal every 250 μsec, which corresponds to two frames in this embodiment, and supplies the signal to the terminal devices A and B via the line 110. This signal becomes a reset signal for the counter decoders 22 and 23 of terminal devices A and B. If the number of terminal equipment is rl, the counter decoder 22.23 counts from 1 to 2n by 1 for each time slot. Here, the terminal device A assumes that the count value of the counter decoder 22 is "
3", data is sent and received and terminal device B
If the data is sent and received when the count value of the counter decoder 23 reaches rn+3, the terminal device fi
A and B exchange data in the same time slot every other frame. In this embodiment, data exchange in a two-multiframe format can also be realized in this manner, and the same effects as in the first embodiment described above can be obtained.

Effects of the Invention As described above, according to the present invention, it is possible to eliminate waste when transmitting and receiving data with a terminal device whose data transmission amount is less than the standard data transmission 1, and to improve the efficiency of data exchange. Furthermore, terminal devices with different amounts of data transmission can be mixed, and the range of use of the digital exchange is expanded.

[Brief explanation of drawings]

112I is a circuit diagram showing the configuration of the time switch circuit 12 of the digital exchange 11 according to the first embodiment of the present invention; FIG. 2 is a diagram showing the connection relationship between the digital text fA machine 11 and the terminal device; 21 is a timing chart for explaining the operation of the digital exchange 11; 411J is a diagram for explaining the basic principle of data exchange of the digital exchange 11; FIG. 5 is a block diagram of the second embodiment of the present invention; 6 is a timing chart for explaining the operation of the second embodiment, No. 7111 is a block diagram of the third embodiment of the present invention, and No. 8 is a timing chart for explaining the operation of the second embodiment.
12I is the connection between the conventional digital AC IA machine 1 and the terminal device. 9121 of the diagram showing vI is a block diagram showing the configuration of the conventional digital exchange 1. FIG. 11...Digital AC IA 1ffi, 12...Time switch circuit, 13...Multi-frame counter,
14... Time slot memory, 15.16... Changeover switch, 17... Connection memory, 18...
・Control unit, 19...Arithmetic circuit, 20...Time slot counter, 21...Multi-frame pulse generation circuit, 22.23...Counter decoder agent Patent attorney Kei Yotsutsu

Claims (1)

[Claims] In a digital switching system to which a plurality of terminal devices are connected and which periodically and sequentially designate the terminal devices to transmit and receive data for each predetermined data capacity, there is provided a standard defined by the period and the data capacity. Identification data output means for periodically outputting identification data for identifying a cycle within each engine corresponding to a frequency determined in accordance with the deviation between the data transmission amount and the data transmission amount of the terminal device; and address data output means for repeatedly outputting a predetermined type of address data every cycle, and for terminal devices whose data transmission amount is less than the standard data transmission amount, the identification data and address data are used for each institution. A digital exchange characterized in that a terminal device can be specified.