JPH02260981A - Character/pattern storing/reproducing device - Google Patents

Character/pattern storing/reproducing device

Info

Publication number
JPH02260981A
JPH02260981A JP1081886A JP8188689A JPH02260981A JP H02260981 A JPH02260981 A JP H02260981A JP 1081886 A JP1081886 A JP 1081886A JP 8188689 A JP8188689 A JP 8188689A JP H02260981 A JPH02260981 A JP H02260981A
Authority
JP
Japan
Prior art keywords
memory
character
video signal
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1081886A
Other languages
Japanese (ja)
Other versions
JPH0787548B2 (en
Inventor
Yoshihiro Nishida
好宏 西田
Keiji Kimura
木村 恵爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1081886A priority Critical patent/JPH0787548B2/en
Publication of JPH02260981A publication Critical patent/JPH02260981A/en
Publication of JPH0787548B2 publication Critical patent/JPH0787548B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To produce an effect like an animation by composing a memory map so that the high-order bit of a memory address for plural pictures may designate the pages of the pictures, and automatically switching a character pattern screen at a constant cycle. CONSTITUTION:When an animation mode command 16, which automatically switches the screen, is inputted, a most significant bit switching circuit 15 automatically switches and reads the most significant bit of the address of a memory 6 at every constant interval of time. When illustrations are stored on the first and second pages of the memory 6, the respective illustrations are alternately superimposed on the signal from a video signal input terminal 1 and outputted. Based on said method, a stored arbitrary character and graphic are read, superimposed on the normal video signal, projected, and when they are utilized for video camera photographing and video editing, the effect can be produced as if they are moving.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、タイトル文字あるいは図形等の両縁パターン
等を記憶し、他の映像に重ねて出力することの出来る文
字・パターン記憶装置に関するものである。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a character/pattern storage device that can store title characters or double edge patterns such as figures, etc., and output them overlapping other images. It is.

〈従来の技術〉 近年、家庭用VTRの普及にともない家庭用ビデオカメ
ラの需要が増加し、家庭用ビデオカメラの多機能化及び
−集掘能等に対する要求が高まってhfc。
<Prior Art> In recent years, with the spread of home VTRs, the demand for home video cameras has increased, and there has been an increasing demand for home video cameras to be multi-functional and have a higher excavation capability.

こnらの機能の中で、タイトル等の挿入を行うインポー
ズ及びテロッパ等は特に要求の多い機能の一つである。
Among these functions, the impose and telopper functions for inserting titles and the like are among the functions that are particularly requested.

以下、従来のタイトル等の挿入を行うテロップ装置に・
ついて、第3図を用いて説明する。第3図において、(
1)はビデオ信号入力端子、(2)は文字・パターン情
報を抽出する検出回路、(3)はビデオ信号入力から同
期信号を分離する同期分離回路、(4)ハシリアルパラ
レル変換回路、(5)はパラレルシリアル変換回路、(
6)はメモリ、(7)は基準クロックの発振回路、(8
)(9)はそ第1ぞnメモリ(6)のアドレスを指令す
る垂直カウンタ、水平カウンタ、αQは同期分離回路(
3)及び発信回路(3)から垂直カウンタ(8)、水平
カウンタ(9)のアップダウンのタイミングを制御する
分局回路、(ロ)はコントローラ、@はスイッチ等のユ
ーザーの指令信号、(至)は文字・パターン情報を他の
ビデオ信号と重畳するための文字重畳回路、α◆はビデ
オ信号出力端子である。
Below, the caption device that inserts conventional titles, etc.
This will be explained using FIG. In Figure 3, (
1) is a video signal input terminal, (2) is a detection circuit that extracts character/pattern information, (3) is a sync separation circuit that separates a sync signal from the video signal input, (4) is a serial-to-parallel conversion circuit, (5) ) is a parallel-to-serial conversion circuit, (
6) is a memory, (7) is a reference clock oscillation circuit, (8) is a reference clock oscillation circuit, and (8) is a reference clock oscillation circuit.
) (9) is the vertical counter and horizontal counter that command the address of the first n memory (6), αQ is the synchronization separation circuit (
3) and a branch circuit that controls the up/down timing of the vertical counter (8) and horizontal counter (9) from the transmitting circuit (3), (b) is the controller, @ is the command signal from the user such as a switch, (to) is a character superimposition circuit for superimposing character/pattern information with other video signals, and α◆ is a video signal output terminal.

まず、文字・パターン信号の主な流れを説明する。ビデ
オ信号入力端子(1)により入力されたビデオ信号は、
同期分離回路(3)により同期信号が作成されると共に
、検出回路(2)により二値化されデジタル信号となる
。このデジタル信号は、シリアルパラレル変換回路(4
)により8ビツト等のデジタル信号となりメモリ(6)
に記憶される。またメモリ(6)に記憶された文字・パ
ターン等の情報である8ビツト等のデジタル信号は、パ
ラレルシリアル変換回路(5)によりシリアルデジタル
信号となり文字重畳回路(2)により本来のビデオ信号
に重畳された形でビデオ出力端子α◆に出力される。
First, the main flow of character/pattern signals will be explained. The video signal input through the video signal input terminal (1) is
A synchronization signal is created by the synchronization separation circuit (3), and is binarized into a digital signal by the detection circuit (2). This digital signal is processed by a serial-parallel conversion circuit (4
), it becomes a digital signal such as 8 bits and becomes a memory (6).
is memorized. In addition, the 8-bit digital signal, which is information such as characters and patterns stored in the memory (6), is turned into a serial digital signal by the parallel-to-serial converter circuit (5), and is superimposed on the original video signal by the character superimposition circuit (2). It is output to the video output terminal α◆ in the form shown below.

以上のような動作を実現するため、本回路の発振回路(
7)で基準クロックを作成し、この基準クロックをシリ
アルパラレル変換回路(4)及びパラレルシリアル変換
回路(5)に供給し変換タイミングを与える。また、こ
のクロックは分周回路αOにより分周された後、メモリ
(6)の下位ビットのアドレス指定カウンタである水平
カウンタ(9)に供給され、メモリ(6)のアドレス指
定を行う。水平カウンタ(9)の桁上げ信号は、メモリ
(6)の1位ビットのアドレス指定カウンタである垂直
カウンタ(8)に供給されメモリ(6)のアドレス指定
を行う。また、コントローラ■は、スイッチ等の指令信
号(2)により文字・パターンの書き込みまたは読み込
みかを指定される。
In order to realize the above operation, the oscillation circuit (
In step 7), a reference clock is created, and this reference clock is supplied to the serial-to-parallel conversion circuit (4) and the parallel-to-serial conversion circuit (5) to provide conversion timing. Further, this clock is frequency-divided by a frequency divider circuit αO and then supplied to a horizontal counter (9) which is a counter for specifying the address of the lower bits of the memory (6), thereby specifying the address of the memory (6). The carry signal of the horizontal counter (9) is supplied to the vertical counter (8), which is a counter for addressing the first bit of the memory (6), to address the memory (6). Further, the controller (2) is designated by a command signal (2) from a switch or the like to write or read characters/patterns.

これによりコントローラ(ロ)は、メモリ(6)、シリ
アJL/ /fラレル変換1m flat (4)、パ
ラレルシリアル変換回路(5)、水平カウンタ(9)、
垂直カウンタ(8)、分局回路Q1、発振回路(7)を
動作または非動作状態にする。
As a result, the controller (b) includes a memory (6), serial JL//f parallel conversion 1m flat (4), parallel to serial conversion circuit (5), horizontal counter (9),
The vertical counter (8), branch circuit Q1, and oscillation circuit (7) are activated or deactivated.

コントローラ(ロ)は、同期分離回路(3)により供給
された同期信号を基準にして、1フイールドの始点で水
平カウンタ(9)、垂直カウンタ(8)のリセットを行
い、画面内のパターン、文字等の位置とメモリ(6)の
アドレスとの相関をとる。
The controller (b) resets the horizontal counter (9) and vertical counter (8) at the start point of one field based on the synchronization signal supplied by the synchronization separation circuit (3), and resets the pattern and characters on the screen. Correlation is established between the positions of the locations and the addresses of the memory (6).

譚贋 〈発明が解決しようとする[嗜) 以上、従来の文字・パターン記憶再生装置について述べ
たが、従来の文字・パター・ン記憶再生装置では、自動
的に一定周期毎に文字・パターン画面を切り替えること
が出来なかった。
The above describes the conventional character/pattern memory/reproduction device. could not be switched.

本発明の目的は、家庭用ビデオカメラ等において、自動
的に一定周期毎に文字・パターン画面を切り替えて、ア
ニメーションの様な効果を出すことが出来る文字・パタ
ーン記憶再生装置を提供す複数両面分のメモリのアドレ
スの上位ビットが画面のページ指定になるようにメモリ
マップヲ構成し、上位ビット切り替え回路を設ける。
An object of the present invention is to provide a character/pattern storage/playback device that can automatically switch the character/pattern screen at regular intervals to produce an animation-like effect in a home video camera or the like. The memory map is configured so that the upper bits of the memory address specify the screen page, and an upper bit switching circuit is provided.

〈作用〉 一定時間毎に上位ビットを切り替えることにより、ペー
ジ即ち文字・パターン画面を切り替えることが出来る。
<Operation> By switching the upper bits at regular intervals, pages, that is, character/pattern screens can be switched.

〈発明の実施例〉 以下、画面数を2画面とした時の本発明の実施例を図面
を用いて説明する。第1図は、本発明による文字・パタ
ーン記憶、再生装置の一実施例を示すブロック図である
。第1図において、(1)はビデオ信号入力端子、(2
)は文字・パターン情報を抽出する検出回路、(3)は
ビデオ信号入力から同期信号を分°離する同期分離回路
、(4)はシリアルパラレル変換回路、(5)はパラレ
ルシリアル変換回路、(6)はメモリ、(7)は基準ク
ロックの発振回路、(8)(9)はそれぞれメモリ(6
)のアドレスを指令する垂直カウンタ、水平カウンタ、
亜はスイッチ等のユーザーの指令信号、(至)は文字・
パターン情報を他のビデオ信号と東壁するための文字重
畳回路、a4はビデオ出力端子、(ロ)は指令信号(6
)及び同期分離回路(3)からの同期信号を入力し、垂
直カウンタ(8)、水平カウンタ(9)のカウント及び
リセットのタイミングやメモリ(6)の読み書きを制御
するコントローラ、(ト)は画面のページ指令である最
上位ビット切り替え回路、Q時は動画モード指令信号で
ある。
<Embodiments of the Invention> Hereinafter, embodiments of the present invention when the number of screens is two will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a character/pattern storage and reproduction device according to the present invention. In Figure 1, (1) is a video signal input terminal, (2
) is a detection circuit that extracts character/pattern information, (3) is a synchronization separation circuit that separates a synchronization signal from video signal input, (4) is a serial-to-parallel conversion circuit, (5) is a parallel-to-serial conversion circuit, ( 6) is the memory, (7) is the reference clock oscillation circuit, and (8) and (9) are the memories (6), respectively.
) vertical counter, horizontal counter,
A is a command signal from the user such as a switch, and (to) is a letter/
A character superimposition circuit for combining pattern information with other video signals, a4 is a video output terminal, (b) is a command signal (6
) and the sync signal from the sync separation circuit (3), and controls the count and reset timing of the vertical counter (8) and horizontal counter (9), as well as the reading and writing of the memory (6); (g) is the screen; The most significant bit switching circuit is the page command, and Q time is the video mode command signal.

第2図は、本発明の文字・パターン記憶再生装置のメモ
リマツプの例で、一般に256にビットと呼ばれている
メモリを水平512ビツト、垂直256ビツトの画面を
2枚分記憶再生する様に構成している。NTSC方式の
信号はIV(垂直走査)は262.5H(水平走査)で
あるが、実際に映像信号が入っている有効期間は約24
0Hであるので垂直ビット数は256で十分である。
Figure 2 shows an example of a memory map of the character/pattern storage/reproduction device of the present invention, which is configured to store and reproduce two screens of 512 bits horizontally and 256 bits vertically using a memory generally called 256 bits. are doing. The IV (vertical scan) of the NTSC system signal is 262.5H (horizontal scan), but the effective period in which the video signal is actually contained is approximately 24
Since it is 0H, 256 vertical bits is sufficient.

自動的に画面を切ゆ替える状態を動画モードと呼ぶこと
にすると、動画モードでない時即ち動画モード指令信号
a・が入力されていない時は従来例と全く同様に文字・
パターン情報の記憶再生動作を行う。この時、指令信号
韓からの画面のページ指令が最上位ビット切り替え回路
に)に与えられ、メモリ(6)のアドレスの最上位を切
り替え、それぞれのページに文字・パターン情報が記憶
再生される。
If we call the state in which the screen is automatically switched the movie mode, when the screen is not in the movie mode, that is, when the movie mode command signal a.
Performs storage/reproduction operation of pattern information. At this time, a page command for the screen from the command signal is given to the most significant bit switching circuit (2) to switch the most significant address of the memory (6), and character/pattern information is stored and reproduced in each page.

動画モード指令4時が入力されると、最上位ビット切り
替え回路(ト)はメモリ(6)のアドレスの最上位ビッ
トを自動的に一定時間毎に切り替えて読み出しを行う。
When the video mode command 4 o'clock is input, the most significant bit switching circuit (g) automatically switches and reads the most significant bit of the address of the memory (6) at regular intervals.

第2図に示し九ようなイラストをメモリ(6)の第1ペ
ージ、第2ページに記憶させておいたとすると、それぞ
れのイラストが交互にビデオ信号入力端子(1)からの
信号に重畳されて出力できる。
If illustrations like those shown in Figure 2 are stored in the first and second pages of the memory (6), each illustration will be alternately superimposed on the signal from the video signal input terminal (1). can be output.

以上、画面数が2画面の場合について説明したが、画面
数が4画面、8画面と増えても同様に考えられる。この
時は、アドレスの最上位ビットだけでな(、上位2ビツ
ト、3ビツトを順次切り替えることにより実現できる。
Although the case where the number of screens is two has been described above, the same can be considered even if the number of screens increases to four or eight screens. This can be achieved by sequentially switching not only the most significant bit of the address, but also the two and three most significant bits.

〈発明の効果〉 以上のように、本願発明によれば、記憶した任意の文字
・図形(タイトル、コメント、イラスト等)を読み出し
、通常の映保信号に重ねて映出し、ビデオカメラ撮影及
びビデオ編集に利用する際に、タイトル、コメ〉・ト、
イラスト等の情報をアニメーションのように切り替え、
あたかもそれらが動いている様な効果を出すことが出来
る。
<Effects of the Invention> As described above, according to the present invention, any stored characters/figures (titles, comments, illustrations, etc.) are read out and displayed overlaid on a normal video signal, allowing video camera shooting and video recording. When using it for editing, please enter the title, comments,
Switch information such as illustrations like animation,
You can create an effect that makes it appear as if they are moving.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明の一実施例を示す図で、第1図
は構成を示すブロック図、第2図はメモリマツプを示す
図である。 第3図は従来の一実施例を示すブロック図である。 2:検出回路  4ニジリアルパラレル変換回路  5
:パラレルシリアル変換回路  6:メモリ  11:
コントローラ  13:文字重畳回路16:最上位ビッ
ト切り替え回路  16:動画モード指令信号 なお、図中、同一符号は同一 または相当部分を示す。
1 and 2 are diagrams showing one embodiment of the present invention, with FIG. 1 being a block diagram showing the configuration, and FIG. 2 being a diagram showing a memory map. FIG. 3 is a block diagram showing a conventional embodiment. 2: Detection circuit 4 Digital parallel conversion circuit 5
:Parallel-serial conversion circuit 6:Memory 11:
Controller 13: Character superimposition circuit 16: Most significant bit switching circuit 16: Video mode command signal Note that in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)ビデオ信号に重畳された文字・パターン情報を二
値化する検出回路、この二値化された信号をパラレル・
デジタル信号に変換するシリアルパラレル変換回路、こ
のパラレルデジタル信号を記憶するメモリを持ち、テレ
ビジョンカメラ等のビデオ信号に重畳された文字・パタ
ーン情報を複数画面分記憶し、このメモリから読み出し
たデータをシリアルデジタル信号に変換するパラレルシ
リアル変換回路、及びこのシリアルデジタル信号を他の
ビデオ信号に加算重畳してビデオ信号出力として得られ
る装置において、複数画面を一定時間ごとに切り替えて
再生することが出来る文字・パターン記憶再生装置。
(1) A detection circuit that binarizes character/pattern information superimposed on a video signal, and converts this binarized signal into parallel
It has a serial-parallel converter circuit that converts it into a digital signal, and a memory that stores this parallel digital signal. It stores character/pattern information for multiple screens superimposed on the video signal of a television camera, etc., and the data read out from this memory. In a parallel-to-serial converter circuit that converts to a serial digital signal, and in a device that adds and superimposes this serial digital signal to another video signal to obtain a video signal output, a character that can switch and reproduce multiple screens at regular intervals. -Pattern storage and playback device.
JP1081886A 1989-03-31 1989-03-31 Character / pattern memory playback device Expired - Lifetime JPH0787548B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1081886A JPH0787548B2 (en) 1989-03-31 1989-03-31 Character / pattern memory playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1081886A JPH0787548B2 (en) 1989-03-31 1989-03-31 Character / pattern memory playback device

Publications (2)

Publication Number Publication Date
JPH02260981A true JPH02260981A (en) 1990-10-23
JPH0787548B2 JPH0787548B2 (en) 1995-09-20

Family

ID=13758931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1081886A Expired - Lifetime JPH0787548B2 (en) 1989-03-31 1989-03-31 Character / pattern memory playback device

Country Status (1)

Country Link
JP (1) JPH0787548B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06197278A (en) * 1992-04-29 1994-07-15 Canon Inf Syst Res Australia Pty Ltd Video movie
JPH06217200A (en) * 1992-04-29 1994-08-05 Canon Inf Syst Res Australia Pty Ltd Portable video animation equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06197278A (en) * 1992-04-29 1994-07-15 Canon Inf Syst Res Australia Pty Ltd Video movie
JPH06217200A (en) * 1992-04-29 1994-08-05 Canon Inf Syst Res Australia Pty Ltd Portable video animation equipment

Also Published As

Publication number Publication date
JPH0787548B2 (en) 1995-09-20

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