JPH02262192A - Liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device that displays images by arranging, for example, liquid crystal display elements in an X-Y matrix.

[Summary of the invention]

The present invention relates to a liquid crystal display device, in which a video signal whose polarity is inverted at predetermined intervals is sampled using a pulse signal corresponding to a horizontal pixel, and when this sampled signal is held, the power supply of a circuit that performs this holding is By shifting the potential at the timing of polarity reversal, the dynamic range of the circuit is effectively utilized, and a good image can be displayed with a simple configuration.

[Conventional technology]

For example, it has been proposed to display television images using liquid crystals (
(See Japanese Patent Laid-Open No. 59-220793, etc.).

That is, in FIG. 5, (1) is an input terminal to which a television video signal is supplied, and the signals from this input terminal (1) are vertically ( Y
It is supplied to the lines L, , L, . . . LLll in the axial direction. Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Furthermore, an m-stage shift register (2) is provided, a clock signal ΦlH+Φ214 with m times the horizontal frequency is supplied to this shift register (2), and a clock signal ΦIl from each output terminal of this shift register (2) is supplied.
++ Drive pulse signal φ sequentially scanned by φ2H
H++ φH2...φ, is the switching element M, =
It is supplied to each control terminal of Mm.

Note that a low potential (Vss) and a high potential (Vnn) are supplied to the shift register (2), and drive pulses of these two potentials are formed.

In addition, each line L1 to Lll+ has a switching element M1□M21.
・・M、、M、、M2□・・・MJlt+ ・・・M
I, M2. , . . . Mnm are connected at one end. Note that n is a number corresponding to the number of horizontal scanning lines. The other ends of these switching elements M, ~Mnm are respectively liquid crystal cells C1l+
Cgl...Target terminal (3) through Cnm
connected to.

Furthermore, an n-stage shift register (4) is provided, and this shift register (4) receives a horizontal frequency clock signal Φ11.
．． Φ2v is supplied, and drive pulse signals Φ95. φv2...φV
7 is the gate line G in the horizontal (X-axis) direction.

...Switching element M + l-M through Gn
Each column in the X-axis direction of nm (!vL+-M+-), (Mz
+~Mg-)... (M-1~Mnm) are respectively supplied to control terminals. In addition, shift register (4
) is also supplied with VS3 and VDD similarly to the shift register (2).

That is, in this circuit, the shift register (2).

(4) As shown in FIG. 6A and B, the lock signal Φ,
, Φ2N+ ΦlV+ Φ2. is supplied. The shift register (2) then outputs φMl to φH1 for each pixel period as shown in FIG.
4), as shown in the same figure, φ9.
~φVn is output. Further, the input terminal (1) is supplied with a signal as shown in FIG.

Then, when φVl+φ, is output, switching elements M1 and M + I-M are turned on,
A current path of input terminal (1) -M, -L, → M11 → C1l → target terminal (3) is formed, and the liquid crystal cell CI+
The signal supplied to the input terminal (1) and the target terminal (
3) is supplied. Therefore, this cell CI+
Charge corresponding to the potential difference due to the signal of the first pixel is sampled and held in the capacity. The light transmittance of the liquid crystal changes depending on the amount of charge. The same process is performed sequentially for cells C1~Cnm, and when the next field signal is supplied, each cell CIl~Cnm
The amount of charge is rewritten.

In this way, the light transmittance of the liquid crystal cells C, .

Furthermore, when displaying on a liquid crystal, its reliability and
AC drive is used to extend life. For example, in displaying a television image, a signal obtained by inverting the video signal is supplied to the input terminal (1) for each field or frame. In addition, in liquid crystal display devices, the signal is
Reversal is performed every horizontal period. That is, as shown in FIG. 6, the input terminal (1) is supplied with a signal that is inverted for each horizontal period and also for each field or frame.

By the way, in such a device, the shift register (2
) The time width of the drive pulse signals φH1 to φH0 output from
There is about ec. On the other hand, when applied to high-vision, for example, the time of the horizontal effective screen period becomes approximately 3 times, and the number of horizontal pixels becomes approximately 3 times, so the time width of the above-mentioned pulse is shortened to approximately □.

On the other hand, the signals passed through the switching elements M1 to Mm during the period of the drive pulse signals φM1 to φH are the lines L1 to φH.
It is supplied to the switching elements M11 to Mnm through Lm, but in this case, the lines L and Lm are supplied with 10 to several 1
There is a wiring capacitance of 0 pF, so the signal charges this capacitance and is supplied to the switching elements M, . . . -Mnm.

And in this case, the charging described above has a signal supply time of 10
Although it can be raised to the signal potential in about 0 nsec, if this time is shortened to -, charging will not be done sufficiently when the signal is at a high potential (white or black), and the displayed image will be unclear and lack contrast. There was a risk that the product would not be obtained. Note that in the case of high-definition, the wiring capacity will further increase.

[Problem to be solved by the invention]

On the other hand, the input video signal is set to drive pulses φ, 1 to φ,
The parallelized signals are sampled and parallelized for each period of
A method is being considered to ensure that the lines L1 to Lm are sufficiently charged by supplying the line L1 to Lm.

That is, in FIG. 7, the video signal supplied to the input terminal (1) is transmitted through the CMO three elements M constituting the horizontal switch means.
al+M, □...M, and drive pulse signals φH1 to φM and d from the shift register (2) are supplied to the control terminals of these elements M1 to M @ 1H, respectively.
, , -d- are supplied.

Signals from these elements M0 to M are connected to buffer amplifiers B□+Big...B, each of which constitutes a holding means.
ath, and the outputs of these buffer amplifiers B m + " B a m are fed back to the inverting input. Signals from these buffer amplifiers B0 to B8 are respectively connected to the three CMO elements constituting the loading means. M,
, M y 2... are supplied to M, and these elements M
> Horizontal blanking pulse ( ) (EL
X and HBLX) are supplied.

Signals from these elements M, 1 to Mb, l are sent to amplifiers Bbl+ Bbz...Bb as buffer circuits, respectively.
The outputs of these buffer amplifiers Bb and -B are fed back to the inverting inputs. Signals from these buffer amplifiers Bb and -B are respectively supplied to lines LI-Lm in the vertical (Y-axis) direction.

Furthermore, the following configuration is similar to the device described in the prior art section.

Therefore, in this device, when a video signal as shown in FIG. 8A is supplied to the terminal (1), the elements M, .
M- is made conductive as shown in FIG.
It is held at B. On the other hand, elements M and 1 to M are made conductive at the timing of horizontal blanking as shown in figure C, and the held signals are supplied (loaded) to lines L and to Lm through buffer amplifiers Bbl to Bbm, respectively. be done. Thereafter, images are displayed in the same manner as in the conventional case.

By the way, in this device, the buffer amplifier Bat~B
a1l and Bbl to Bbm are amplifiers with a gain of 1, and are configured, for example, as a TPT as shown in FIG. In the figure, a differential amplifier consisting of NM (is elements Nl, NZ) is provided, and a signal is input (Vin) to the gate of one of the elements N2, and the elements N, NZ.

The drains of N2 are connected to each other via a current mirror circuit of three PMO elements P, P2. , is connected to the power terminal of the . The drain of this element N2 is PMO3 element P
, and the drain of this element P3 is connected to the gate of .

. The source of element P3 is connected to the gate of NMO3 element N3, and the drain of element N3 is connected to the power supply terminal of VDD. Further, the source of element P3 is connected to the drain and gate of NMO3 element N4, the source of this element N4 is connected to the drain of PMO3 element P4, and the gate and source of element P4' are connected to the gate of PMO3 element P5. , the source of this element P5 is connected to the power supply terminal of VSS. And element N
The source of element N1 and the drain of element P5 are connected to each other, and this connection point is connected to the gate of element N1, and a signal is output (Vout) from this connection point. Further, the source of element P3 is connected to the gate of NMO3 element N, , the drain of element N is connected to the power supply terminal of VDD, and the source of element N is connected to the drain of element N2 via capacitor C. Connected. Note that elements N6 to N
11 is a bias current source, and the current of a constant current source 2 is passed through an element N forming a current mirror circuit.

Therefore, in this circuit, the element N+ N z N e
P+P2 constitutes a first stage high gain amplifier, elements P3P4N4N6 constitute a next stage amplifier and level shift, and element N5PS constitutes an output buffer. Note that elements N, N, and capacitor C are a phase compensation circuit.

However, in the above-described device, the polarity of the signal supplied to the input terminal (1) is inverted at predetermined intervals as described above. For this reason, the buffer amplifiers B1 to B□+ mentioned above
For example, as shown in Fig. 10, an extremely wide dynamic range is required to pass the entire polarity-inverted signal, making circuit design and element formation difficult and generally difficult. In the buffer amplifier, as shown in the figure, a predetermined cutoff voltage V is applied to the VSS side. There is a saturation voltage ■6 on the side, and the power supply voltage ■ is supplied to the buffer amplifier. D+
VSS has these ■ in the dynamic range. , ■8 is required. For this reason, when the dynamic range is widened, 1Vnn Vssl becomes extremely large, requiring each element to have a high withstand voltage, which may make circuit design and element formation even more difficult.

This application was filed in view of these points.

[Means to solve the problem]

The present invention provides a plurality of first signal lines Ll, L2...Lm arranged in parallel in the vertical direction, and a plurality of second signal lines G, G2...Lm arranged in parallel in the horizontal direction. . .On are provided, and these first . In a liquid crystal display device in which liquid crystal cells C1, Cnm, . A plurality of horizontal switch means (CMO 3 elements M 11 + M 11
2...M3, ) and a plurality of hold means (buffer amplifiers B a I + B @Z...B,), and the power supply potential supplied to the holding means is shifted by a predetermined potential at the timing (φ1, φ2) when the polarity of the input video signal is reversed. This is a liquid crystal display device characterized by the following.

[Effect]

According to this, by shifting the power supply potential of the circuit at the timing of polarity reversal, the dynamic range of the circuit can be apparently expanded, and signal processing can be performed using ordinary circuits without using high-voltage elements. It can be carried out.

〔Example〕

In FIG. 1, the buffer circuit (amplifier) B of the device shown in the above-mentioned problem is shown.
For bm, its power supply V. and VSS lines are switches (6ao) (6as) and (6bn) respectively
(6bs) is connected to the movable contact. One fixed contact of these switches (6an) (6bn) is connected to VDDI.
and the other fixed contact is connected to VDD2, and one fixed contact of the switch (6as) (6bs) is connected to VSSI, and the other fixed contact is connected to VS! 12
connected to. And these switches (6an) (
6as) and (6bo) (6bS) are the terminals (
It is controlled by control signals φ and φ2 from 7a) and (7b). Note that the switches (6ap) (6as) and (6bo) (6bs) are actually composed of electronic switches using switching elements.

Therefore, in this device, the buffer amplifier Bat~B
The characteristics of am+ Bb+ to B can be made as shown in FIG. 2, for example, and the control signal φ1. By switching φ2 in accordance with the polarity of the input signal, signal processing can be performed satisfactorily even in a circuit with a narrow dynamic range.

In this way, according to this device, by shifting the power supply potential of the circuit at the timing of polarity reversal, the dynamic range of the circuit can be apparently expanded, and the signal can be generated using a normal circuit without using high-voltage elements. It is something that can be processed.

Further, in the above-described device, the signals φ and φ2 are formed as shown in FIG. 3, for example. In other words, A and B in the same figure
The input video signal and horizontal blanking pulse (
HIL, K), the signals φ1 and φ2 have their entire phases inverted, and the signal φ1 has a pulse (H++tx
), the phase is switched at the trailing edge of ), and φ2 is a pulse (Hgtx)
The phase is switched at the leading edge of .

As a result, the signals sampled and held by the switching elements M1 to Mam are transferred to the switching elements M
B, ~M when synchronized and loaded into each signal line L, ~Lm°, the respective buffer amplifiers B, ~B
, l, l, and Bbl~B can be matched to the supplied signals, and since the signals supplied to buffer amplifiers B~B are held during the pulse (H++Lx) period, There is no problem even if the signal φ2 is simply the opposite phase of the signal φ1.

Furthermore, in the above explanation, it is assumed that the polarity of the input video signal is inverted every horizontal period, but if this is done every field, the signals φ and φ2 will become as shown in FIG. 4. That is, in this case, the signals φ and φ2 are switched at the leading edge of the vertical blanking period (V++tx), and
At this time, the signals φ1 and φ2 are in phase.

〔Effect of the invention〕

According to this invention, by shifting the power supply potential of the circuit at the timing of polarity reversal, the dynamic range of the circuit can be apparently expanded, and signal processing can be performed using an ordinary circuit without using high-voltage elements. It is now possible to do this.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 to 4 are diagrams for explaining the same, and FIGS. 5 to 10 are diagrams for explaining a conventional apparatus. L1~Lm are vertical signal lines, 01~Gn are gate lines, M
a + ~M a r + M b + ~ M b m
+M++~Mnm is a switching element,
B0~B a+n+ B b l ””' B l+
+% is buffer amplifier, C, 1~Cnm is liquid crystal cell, (
1) (3) (5) (7a) (7b) are terminals, (2)
(4) is a shift register, (6an) (6as)
(6bo) (6bs) are switches.

Claims (1)

[Claims] A plurality of first signal lines arranged in parallel in the vertical direction and a plurality of second signal lines arranged in parallel in the horizontal direction are provided, and these first, In a liquid crystal display device in which a liquid crystal cell is provided at each intersection of a second signal line via a selection element, a plurality of horizontal switch means are sequentially turned on by pulse signals sequentially generated from a horizontal scanning means; and a plurality of hold means to which an input video signal whose polarity is inverted periodically is supplied via the horizontal switch means, and a power supply potential supplied to the hold means is such that the polarity of the input video signal is inverted. A liquid crystal display device characterized in that the potential is shifted by a predetermined potential depending on the timing.