JPH0226260A - Control of multiplex dc/dc converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a multiple DC
/Relates to a method of controlling a DC converter.

(Prior Art) Conventionally, in order to control multiple DC/DC converters, multiple unit DC/DC converters are connected in series or in parallel, and the power of each unit is controlled in order to reduce current ripple on the secondary side of the transformer. A method is adopted in which the control pulses of semiconductor elements (switching elements) are controlled with a certain phase difference. For example, in a series double DC/DC converter,
Generally, a method is used in which the control pulses have a phase difference of 90'' electrical angle.

FIG. 8 and FIG. 9 are configuration diagrams when a series double DC/DC converter is applied to an auxiliary power supply device for a DC electric vehicle.

Here, as shown in FIG. 8, the double DC/DC converter 70 includes two unit converters 71 and 72, an output smoothing actuator 9, and an output capacitor 8 with the same capacity.
0.81. Further, each unit converter 71, 72 includes DC-AC converting means 73, 74 and AC-DC converting means 75 connected to their output sides.
76, each DC-AC conversion means 73
and 74 and each AC-DC conversion means 75 and 76 are connected in series.

As shown in FIG. 9, the DC-AC conversion means 73 is a GT in which a series circuit of input filter capacitors 731 and 732 and free-wheeling diodes 735 and 736 are connected in antiparallel.
O thyristor, G T Oz, G T O* (7
) series circuit and the primary winding of the transformer 77, each of the above series circuits is connected in parallel, and between the input filter capacitors 731 and 732 G T Oz , G
The primary winding of a transformer 77 is connected between T and Ox.

Further, the DC-AC conversion means 74 also includes a series circuit of input filter capacitors 741 and 742 and a commutating diode 745.
゜746 connected in anti-parallel G T Oa =
It is composed of the series circuit of G T O4 and the primary winding of the transformer 78, and each of the above series circuits is connected in parallel, and the connection between the input filter capacitors 741 and 742 and the a'ro
, a'rO4 is connected to the primary winding of a transformer 78.

The AC-DC conversion means 75 is composed of a secondary winding of a transformer 77 and diodes Dz, Ds, and the AC-DC conversion means 76 is composed of a secondary winding of a transformer 78 and diodes Da, D. It is composed of 4. The cathode sides of diodes D1 and D2 and the cathode sides of diodes D2 and D4 are connected, respectively, and the cathode sides of diodes D3 and D
The connection point on the cathode side of No. 4 is connected to the intermediate tap of the secondary winding of the transformer 77 of the AC-DC conversion means 75.

The anode side of the diodes D z and D z is connected to the transformer 7
7, and the cathodes of diodes D s and D 4 are connected to its intermediate tap.

The anodes of the diodes D, , D, are connected to both ends of the secondary winding of the transformer 78, and their middle taps are connected to the output terminal C of the DC/DC converter 70. Further, the cathode connection point of the diodes Dz and Dz is the positive output of the AC-DC converting means 75, and the intermediate tap of the secondary winding of the transformer 77 is the negative output of the AC-DC converting means 75. Similarly, the cathode connection point of the diodes D- and DI is the positive output of the AC-DC conversion means 76, and the intermediate tap of the secondary winding of the transformer 78 is connected to the AC-DC conversion means 76.
The negative side output of

Further, the positive output side of the AC-DC conversion means 75 is connected to the output terminal a via an output smoothing reactor 79.
Furthermore, output capacitors 80 and 81 are connected in series between output terminal a and output terminal C.

One point between the output capacitors 80 and 81 is connected to the output terminal.

Hereinafter, the operation of the double DC/DC converter 70 will be explained in the ninth section.
This will be explained using figures.

First, DC power supplied from the pantograph 82 to the double DC/DC converter 70 via the reactor 83 which is an input filter is converted into AC power by the DC-AC converting means 73, 74, and then the AC-DC converting means 75 .76
is reconverted into DC power. This power is.

It is supplied to a load (not shown) from output terminals a, b, and c via an output smoothing reactor 79 and capacitors 80 and 81.

Here, the input voltage (overhead line voltage) Es is the reactor 83
The capacitors 731, 732, 741, and 742 are each charged with Es/4 via. Now, the DC-AC conversion means 73. It is assumed that control is performed with a phase difference of 90° between the DC-AC conversion means 74. Further, each GTO operates on and off at a switching frequency f, and the DC-AC conversion means 73
The phase difference between GTO1 and GTOz of , and the phase difference between GTO3 and GTO4 of the DC-AC conversion means 74 are each 180°, and the conduction rate of each GTO at this time is α. shall be.

When G T Ox is turned on, the voltage of capacitor 731 becomes
When GTO□ is turned on, the voltage of capacitor 732 is alternately applied to the primary winding of transformer 77, and an alternating current voltage is generated in the secondary winding of transformer @11. Similarly, GTO.

When G T O4 is alternately turned on, an alternating voltage is generated in the secondary winding of transformer 78. An AC voltage having an average value expressed by the following equation is generated in the secondary winding.

nEsα/4...(1) where n
is the turns ratio of the transformer.

This voltage causes a current to flow in the secondary winding, and this alternating current flows through the diodes D L , D z and D a , D 4
After being rectified by and smoothed by reactor 79.

Supplied to terminals a, b, and c. Note that if the average DC output voltage at this time is Ea, then Ea is the capacitor 80.8
Since the voltages are equally divided by 1, the voltage between terminals a and b and the voltage between terminals s and c are the same Vd.

Here, Eo is nE+sαE from equation (1). =□×2...(2),
Further, when the above equation is modified, it becomes as follows. Therefore, it can be seen that the conduction rate α is proportional to the average DC output voltage EII and inversely proportional to the input voltage Es.

FIGS. 10 and 11 show that Vm is the intermediate tap of the transformer secondary winding and the cathode voltage of diodes D1 to D4, ID is the current flowing through each diode, and the output voltage of the double [)C/DC converter 70 is Vo, G TOL ~G T
These are operation waveform diagrams of each part when the current flowing through O4 is IGt~G4 and the current flowing through reactor 79 is ID (IL). Figure 10 shows the case where α>0.5, and Figure 11 shows the case where α The case of <0.5 is shown in each case.

Further, FIG. 12 is a block diagram showing a conventional control circuit of the dual DC/DC converter 70.

In the figure, 1 is a subtracter, and this subtracter 1 is a double D
The detected output voltage value Vd of the C/DC converter 70 and its set value Vd'' are input, and the deviation thereof is output to the AVR (automatic voltage regulator) 2. The AVR 2 sets the input which is the above deviation to zero. A certain voltage level VAVR is outputted to the comparators 41 to 44 as shown in FIG.
The sawtooth wave generator 31 generates a sawtooth wave Vs with a frequency of 2f that is synchronized with the switching period L/f of the TO and has a phase difference of half a period. The device 32 outputs the sawtooth waves to comparators 43 and 44, respectively.

The comparators 41 to 44 compare the input voltage level output of the AVR 2 with the sawtooth waves of the sawtooth wave generators 31 and 32 to generate on/off signals for the GTO.
1.42 sends the above on/off signal to the pulse distributor 51,
Comparators 43 and 44 output the on/off signals to the pulse distributor 52, respectively. and.

The pulse distributor 51 outputs a switching signal to G T O1 and G T O2, and the pulse divider 52 outputs a switching signal to G T O3 and G T O4.

Note that FIG. 13 is a time chart showing how the switching signal is generated.

In this way, in the conventional control method of the DC/DC converter 70, the voltage level output of the AVR 2 and the sawtooth wave generator 31 are
．． It is configured to perform switching of each GTO by comparing 32 sawtooth waves, and AVR2 performs DC/DC switching.
When performing control to keep the average output voltage Eo of the converter 70 constant, it operates to eliminate fluctuations in the output voltage Eo with respect to fluctuations in the input voltage Es. For example, when the average output voltage E0 increases due to an increase in the input voltage Es, the AVR2 operates to narrow the conduction rate α and maintain the average output voltage E0 at its original state. .

(Problem to be solved by the invention) However, in such a conventional control method, the input voltage Es
When a fluctuation occurs in the output current I OOL or the output voltage Vd, the output of the AVR2 changes only when the output current I OOL or the output voltage Vd changes, and the output of the AVR2 changes the conduction rate α, so the output in response to the input fluctuation changes. The response is slow, and as shown in Figure 14, the output voltage E changes transiently due to control delay.
There was a problem in that o fluctuated, which adversely affected the load.

The present invention has been proposed in order to solve the above-mentioned problems, and in response to fluctuations in the input voltage of a multiplex DC/DC converter, a new current flow that corresponds to the input voltage fluctuations is provided before the AVR operates. Multiplex DC/D that can provide a stable output by suppressing transient output voltage fluctuations when the input voltage Es fluctuates.
The purpose of this invention is to provide a method for controlling a C converter.

(Means for Solving the Problems) The present invention focuses on the fact that there is a certain relationship between the conduction rate and current ripple of a DC/DC converter with respect to the input voltage of a multiplex DC/DC converter, and the current ripple and current ripple are A waveform pattern representing the relationship between conduction rates is set, the conduction rate is determined by comparing this waveform pattern with the current, and the switching element of the DC-AC conversion means is turned on and off based on this conductivity rate. This was done based on the knowledge that if this was done, it would be possible to respond to input voltage fluctuations without any control delay.

That is, the present invention inputs the voltage setting value and detected value of the multiple DC10C converter to an automatic voltage regulator.

A correction signal is superimposed and synthesized on the output of this automatic voltage regulator in synchronization with the switching frequency of the DCODC converter, and this synthesized signal is compared with the output current value of the DC10C converter, and the switching is performed based on the fog comparison signal. It is characterized by turning the element on and off.

This correction signal is characterized in that it is a signal expressed as a signal according to a current ripple value corresponding to the conduction rate of the switching element, and here, this correction signal is made as follows. That is, in the case where the multiplex DC/DC converter is a double type, the correction signal is applied during the period from when the switching element is turned on to 1/2 switching period.

8 fL (α: conduction rate of the switching element determined from Eo and the input voltage of the double DC10C converter.

Eo: Average output voltage of double D C10C converter.

the switching frequency in the f-knee switching element,
L: the inductance on the output side of the double DC C10C converter).
It is preferable to use a signal according to fL.

(Function) According to the present invention, the output voltage setting value and output voltage detection value of the multiplex DC/DC converter are input to the automatic voltage regulator, and the automatic voltage regulator maintains a constant voltage such that the input is zero. Output the level. On the other hand, a correction signal synchronized with the switching frequency of the switching element of the DC-AC conversion means is superimposed and synthesized on the voltage level of the automatic voltage regulator, and then this synthesized signal and a detection signal corresponding to the current of the multiple DC/DC converter are detected. The signals are compared.

Based on this comparison result, each switching element of the DC-AC conversion means is turned on or off, and the multiple DC/DC converter is controlled.

That is, in the present invention, by instantaneously obtaining a predetermined current conductivity using the correction signal before the automatic voltage regulator operates when the input voltage fluctuates, transient fluctuations in the output voltage when the input voltage fluctuates are prevented. .

(Example) First, two basic principles of the present invention will be explained in FIG. 9 and FIG.
This will be explained based on FIG. 0 or FIG.

First, the relationship between the conductivity α of the switching element and the current ripple will be considered.

(If α≧0.5) Figure 10 shows the case where α≧0.5, β=α−0,5...(6) Then, the secondary current ripple ΔI of the transformer 77.78.

teeth.

Here, α is the conduction rate of each GTO as described above, and f
is the switching frequency per -GTO, and L is the inductance of the output smoothing reactor 9. In addition, Eo is the average output voltage of the multiplex DC/DC converter, Vp is the voltage of the transformer secondary winding, and Vp and Es are the transformer 27.28
There is a relationship between Es vp= (8) and the turns ratio n.

In addition, the average output voltage Eo can also be expressed as Eo=2Vpα, so equation (7) becomes 4 α L, where K 1 = (1-α) (2α-1)/4
It is α.

(In the case of α<0.5) Figure 11 shows the case of α<0.5, and the current ripple Δ
becomes , where K z = (1-2α)/4.

Figure 3 shows α and K z using equations (9) and (10).
In this figure, which is a graphical representation of the relationship between K (1
Equation 0) corresponds to the correction signals of Equations (4) and (5). Furthermore, there is a relationship between the primary current 11 of the transformer 77, 78 and the secondary current 2 as follows: I=IL/n, that is, ΔI,=ΔI 1/n−(11). In Figure 3, even when the vertical axis is ΔWork 1, the characteristics are similar to those in the same figure.

When the input voltage Es changes, the output voltage Ea can be kept constant by changing the conduction rate α according to the amount of change, as shown from equation (3). This is the input voltage E
If s is known, its conductivity rate α is uniquely determined.9 Once the conductivity rate α is determined.

This means that the current ripple ΔI2 is uniquely determined from the equation (9), Do) or FIG.

That is, by using the pattern shown in FIG. 3 as a correction value, it is possible to determine the conduction rate α, that is, the control pulse width of the GTO, which is instantaneously required in response to fluctuations in the input voltage Es.

In addition, since there is a relationship expressed by equation (11) between the primary current 11 of the transformers 77, 78 and the secondary current 2, the above consideration can be applied to the primary current 11 of the transformers 77, 78 and the current ripple This also applies to 1.

Next, an embodiment of the present invention based on the above principle will be described with reference to the block diagram of the control circuit shown in FIG.

In the figure, 1 is a subtracter, and this subtracter 1 is the 8th subtracter.
The output voltage detection value Vd and its set value Vd' of the double DC/DC converter 70 shown in the figure are input, and the deviation thereof is output to the AVR (automatic voltage regulator) 2. AVR2 outputs a certain voltage level VAVR to adder 3 so that the input which is the above deviation becomes zero. This voltage level vA
vR is the DC-AC conversion means 73, 74 shown in FIG.
The average current is set to flow through each GT○.

On the other hand, this adder 3 has a pattern waveform Vp corresponding to FIG. 3 with a tact synchronized with the switching period of each GTO.
at is input. This pattern waveform Vpat is the third
As shown in the figure, the vertical axis is the current flux/pull ∆ 2/2 or ∆
11/2, and the horizontal axis is α; The waveform has the same shape as the pattern with tf, and the output voltage level VA! IIH
This is a voltage signal that is added to and causes YGT@+ΔΔ1/2 to flow through each GTO.

Therefore, the magnitude of ΔIa/2 or ΔI/2 is
In the period from when T○ is turned on to 1/2 switching cycle.

Tu 2t E.

8・TufL, so that the value is proportional to 1-2 αEo 8 fL, and in the period from exceeding 1/2 switching period to 1 switching period, (To-t) (2t Tu) E.

8t-Tu fL So, (1-α) (2α-1) E.

8α fL A voltage signal having a value proportional to fL is added to and synthesized to obtain the primary current detection value Il or the secondary current detection value Process 2.
It would be better to compare it with.

Here, t represents the time since each GTO is turned on, and Tu represents the switching period of each unit converter 71, 72. Therefore, there is a relationship between Tu and f: 2 Tu=L/f.

Now, in FIG. 4, the adder 3 adds and synthesizes the voltage level V^VR and the pattern waveform ■pat, and the synthesized waveform V
c is output to the comparator 4. In addition, the primary side current detection value I0 or the secondary side current detection value 2 of the transformer 77, 78 is also input to the comparator 4, and the comparator 4 receives these detected values □
Alternatively, it compares the waveform 2 with the composite waveform Vc, and outputs the comparison result to the pulse distributor 5.

The pulse distributor 5 distributes and outputs switching pulses for each GTO. These switching pulses turn on the GTO in the tact portion of the pattern waveform Vpat,
G at the point where the detected value 11 or Is exceeds the composite waveform Vc.
This is to turn off the TO.

FIG. 5 is a time chart showing the relationship between the composite waveform Vc and the primary or secondary current waveforms of the transformers 77 and 78 in FIG. 9, and the relationship between these and the output of the comparator 4.

That is, in the present invention, when the input voltage Es fluctuates, the current flow 1 or It also changes and its ripple also fluctuates. This is to turn off.

FIG. 6 shows the output power P of the double DC/DC converter 70,
, while switching the GTO with the average output voltage Eo and the conduction rate α1, the input voltage Es changes in the direction of decreasing, so the transformer-secondary current xi (or In this figure, which is a graph showing how the secondary current I2) changes, the vertical axis represents the electric current, and the horizontal axis represents the conduction rate α.

That is, due to a decrease in the input voltage Es.

The output ripple ΔXX (ΔIi) also changes, and the conduction rate changes from α1 to αs. Here, the conductivity α2 after the change is E
The same output power Pa as before the decrease in s (when the conduction rate was α1) is generated. In other words, without adjusting the output of the AVR 2, the decrease in the input voltage Es can be compensated for by increasing the conductivity α while keeping the average output current Ia of the double DC/DC converter 70 the same. , the average output voltage Eo is kept constant.

In this way, according to the present embodiment, even if the input voltage Es of the double DC/DC converter 70 changes, the conductivity α is adjusted to the change in the input voltage Es by pattern correction without adjusting the output of the AVR 2. Since it is automatically corrected to the later new conductivity α, a very fast response can be obtained. Note that FIG. 7 shows the response of the output voltage level VAVR and the output voltage Eo of the AVR 2 to fluctuations in the input voltage Es in this embodiment.

Next, the above embodiment will be explained in more detail with reference to the block diagram of the control circuit shown in FIG. In addition, in Figure 1,
Components that are the same as those in No. 12@ are given the same numbers as in the same figure.

An address encoder 12 connected to a clock generator 11 transmits GTo to ROMs (read only memories) 141 and 142 via an address bus 13.
1. Output an address signal synchronized with each switching period Tu of GTOz, GTO-, and GTO4.

Of these, the ROM 141 stores a pattern of the function waveform (see Fig. 3) corresponding to the primary current pull Δ1 of the transformer 77. Data in which the angles differ by 180° are stored. These ROM141, 142
outputs the function waveform as a digital signal to each data bus 151, 152 based on the address signal from the address bus 13.

D/A (digital/analog) converter 161 or 1
62 converts these digital signals into analog signals, and then converts them into analog pattern waveforms Vp with tact.
at to adders 171, 172 or adders 173, 174
Output each.

On the other hand, the subtracter 1 inputs the detected output voltage value Vd of the double DC/DC converter 70 and its set value Vd'' and outputs the deviation thereof to AVH2. AVH2 sets the input which is the above deviation to zero. The voltage level VAVR is outputted to adders 171 to 174 in this manner.

Next, adders 171, 172 and 173.174
The analog pattern waveform Vpat and the voltage level output VAVR from the /A converters 161 and 162 are added, respectively, and the addition result Vc is sent to the comparators 41, 42 and 43, 4.
4 respectively.

In addition to the addition signals Vc from the adders 171 to 174, the comparators 41 to 44 also receive the addition signals GTO, GTo2, . GTo3.
Current flowing through GT O4 I G1. IGz, 103
g A signal corresponding to IG4 is input. Then, the comparators 41 to 44 pulse-distribute a signal that turns on each GTO in the tact portion of the analog pattern waveform Vpat and turns off each GTO at the point where the signal corresponding to the GTO current Ia1 to G4 exceeds the addition signal Vc. output to devices 51 and 52. Then, the pulse distributors 51 and 52 output the comparators 41, 42, 43, and 44 output voltage signals tt G T O1, a T O
x and G T Oa - G T Oa and distributed output.

FIG. 2 shows a waveform obtained by adding and synthesizing the output voltage level VAVR of AVH2 and the pattern waveform with tact Vpat for each of unit converters 71 and 72, and the primary side (or secondary side) current switch 1 of transformer 77, 78. (or It
) relationship with waveforms, and these and a'rox.

It is a time chart showing the relationship between G T Oz and the switching signals of G T O3 and G T O4.

In the above embodiment, a series double DC/DC converter was explained in which the input capacitor was divided into four main circuit configurations as shown in FIG. The present invention is also applicable to common use, to serial multiplexing of two or more, and to other parallel multiplexing DC/DC converters.

Further, in the above embodiment, the voltage level output VA of AVH2
Composite waveform Vc of II and pattern waveform Vpat with tact
Although the analog method was used to compare the transformer-next-side current I control, equivalent control can also be performed using a digital method.

Furthermore, the secondary current Iz of the transformer may be used as the current to be compared with the composite waveform Vc.

(Effects of the Invention) As described above, in the present invention, a correction signal synchronized with the switching frequency of the switching element of the DC-AC conversion means is superimposed and synthesized on the output of the AVH, and this synthesized signal and
By comparing the output detection signal of each DC-AC conversion means or the input detection signal of the AC-DC conversion means and turning on/off the switching element based on the comparison signal, the input voltage can be adjusted before the AVR operates. Since it is possible to provide a new conduction rate that corresponds to fluctuations, multiple DC/DC converters can be controlled simply by comparing the set voltage and the output voltage of multiple DC/DC converters using AVR, unlike conventional methods. compared to how to.

The output response to input fluctuations is fast, and the output voltage E
This has the effect of eliminating the negative impact on the load due to variations in o.

Furthermore, when a signal corresponding to the output current ripple value of the multiplex DC/DC converter determined from the DC input voltage and the conduction rate of the switching element is adopted as the correction signal,
The above effect is particularly remarkable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control circuit for explaining one embodiment of the present invention in detail, FIG. 2 is a time chart for explaining the operation of the control circuit shown in FIG. 1, and FIGS. The figure is a graph for explaining the present invention in detail, FIG. 4 is a block diagram showing a schematic configuration of a control circuit in an embodiment of the present invention, and FIG. 5 is a graph showing the operation of the control circuit shown in FIG. A time chart for explanation; FIG. 7 is a diagram showing the output response of the present invention; FIGS. 8 and 9 are configuration diagrams of a double DC/DC converter to which the present invention and the conventional example are applied; FIG. 10 11 is a time chart for explaining its operation, FIG. 12 is a block diagram of a control circuit in the conventional example, FIG. 13 is a time chart for explaining its operation, and FIG. 14 is an output in the conventional example. It is a figure which shows a response. 1... Subtractor 3... Adder 5... Pulse distributor 11... Clock generator 12... Address encoder 141.142... ROM 161.162... D/A converter 41 ~44...Comparator 13...Address bus 151.152...Data bus 171-174...Adder 51.52...Pulse distributor 2...AVR (automatic voltage regulator) 4 ...Comparator

Claims (3)

[Claims] (1) Each unit DC/DC of a multiplex DC/DC converter in which two or more sets of unit DC/DC converters each composed of a DC-AC conversion means and an AC-DC conversion means are connected.
Regarding the DC converter, the DC output is adjusted by controlling the conduction rate of the switching elements of each of the DC-AC conversion means, and the phase difference is adjusted for the firing timing of the switching elements between the DC-AC conversion means. AC of each unit DC/DC converter
Multiplex DC/D that obtains DC output from the output side of DC conversion means
In the control method of the C converter, the voltage setting value and the voltage detection value of the multiplex DC/DC converter are input to an automatic voltage regulator, and a correction signal synchronized with the switching frequency of the switching element is supplied to the output of the automatic voltage regulator. The combined signal is then compared with the output side AC current signal of each of the DC-AC conversion means or the input side AC current signal of the AC-DC conversion means, and the switching element is controlled based on this comparison signal. A method of controlling a multiplex DC/DC converter characterized by turning it on and off. (2) The correction signal is a multi-D
2. The method of controlling a multiplex DC/DC converter according to claim 1, wherein the signal corresponds to an output current ripple value of the C/DC converter. (3) When the multiplex DC/DC converter is a double DC/DC converter, the correction signal during the period from when the switching element is turned on until 1/2 switching cycle is [(1-2α)/8]・(E_0/fL) (E_0: average output voltage of double DC/DC converter,
α: conduction rate of the switching element determined from E_0 and the input voltage of the double DC/DC converter, f: switching frequency in one switching element, L: double DC
/ inductance on the output side of the DC converter), and in the period from exceeding 1/2 switching period to 1 switching period, [(1-α)
(2α-1)/8]·(E_0/fL) The method for controlling a multiplex DC/DC converter according to claim 2, wherein the signal corresponds to (2α-1)/8]·(E_0/fL).