JPH02263246A - Logic analyzer - Google Patents

Abstract

PURPOSE:To attain the detailed timing analysis of the action information on an information processor with high resolution by connecting a counter between the clock/trigger generators and a data process/control part and applying a trigger action in the period of duration of an optional input pattern regardless of a sampling period. CONSTITUTION:The period of duration of an input pattern S10 is set by the counter control signal received from a data process/control part 7 with a key operation, etc., and the data information. At the same time, the period of duration of the pattern S10 is counted up a counter 12 in a clock period of a clock generator 3 with a write clock S3 and a track stop signal S4 received from a trigger generator 4. Then a trigger output control signal S127 is sent back to the part 7 at the set time. Thus the trigger can be applied in the period of duration of the optional action information regardless of a sampling cycle. As a result, the analyzing time is shortened for a phenomenon having the low reproducibility and at the same time the detailed timing analysis is attained with high resolution.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic analyzer that detects the logic level of a multi-channel digital signal every clock, stores it in a memory in time series, and analyzes the logic level. [Conventional technology]

FIG. 2 is a block connection diagram showing the configuration of the conventional logic analyzer LA shown in, for example, the electronic magazine "Electronics" Vol. 27, No. 12, 1177-1188. The information processing device to be analyzed, SIO, receives operational information including address information, data information, control signals, status signals, error information, etc., which is manually input from the information processing device 10 to be analyzed to the logic analyzer LA. 2 is a sampling circuit that samples the output signal S1 of the comparator 1; 3 is a signal corresponding to the external clock of the output signal S1 of the comparator 1 and the data processing/control unit 7; A clock generator 4 generates a clock S3 based on the internal clock and clock setting information S37 from the input data S2° clock S3 and a trigger trace setting information S47 from the data processing/control unit 7. and a trigger generator 5 for setting and determining trace conditions, 5 is a write clock from the trigger generator 4, a trace stop signal S4, information 357 from the data processing/control unit 7, etc., and generates address information and read/write information of the memory circuit 6. A memory control circuit 6 generates the sampled input data S2 and address information. A memory circuit 7 stores read/write information etc. based on S5 or outputs the stored data, and reads information S6 from the memory circuit 6, processes the information, and displays and records timing charts, disassembly lists, etc. or
It is possible to store the processed data in an auxiliary storage device such as a floppy disk, output the processed data to the outside, or use a clock generator 3. Trigger generator 4. This is a data processing/control unit that sends and receives setting information to and from the memory control circuit 5. 8 is setting conditions and control information S for the data processing/control unit 7
7 is an operation key, 9 is a CRT display that displays information such as the timing of the information processing device 10 analyzed by the data processing/control unit 7, and 1 is a video printer that can print a hard copy of the information. Next, the operation will be explained. The logic analyzer LA generally has two types of functions: a logic timing analyzer for the purpose of hardware analysis and a logic state analyzer that mainly monitors software. Since both are almost the same in terms of hardware, the logic timing analyzer will be explained here. Address information of the information processing device 10 to be analyzed. data information, control signals, status signals. Operation information 310 such as error information is input to the sampling circuit 2 via a comparator of the logic analyzer LA. On the other hand, among the output signals S1 of the comparator 1, the clock generation signal is input to the clock generator 3, and information processing is performed according to the clock generation conditions set by the clock setting information 837 etc. sent from the data processing/control unit 7 in advance. A clock S3 synchronized with the internal operation of the device 10 is generated and sent to the sampling circuit 2 and trigger generator 4. After sampling the output signal S1, this sampling circuit 2 becomes the input data of the memory circuit 6, and a part of the data goes to the trigger generator 4, and the data processing/control unit 7
The trigger trace setting information S47 sent from the trigger trace setting information S47 is compared with trigger trace conditions such as a specific command, specific data, and specific address, and a write clock and trace stop signal S4 is generated, which is input to the memory control circuit 5. be done. In the memory control circuit 5, the write mode, trigger stop, and delay information S57 sent in advance from the data processing/control unit 7
Accordingly, the write mode, trigger stop, and delay are set, and the write clock and trace stop signal S4 count up the internal address counter every time the write clock S4 enters according to the setting conditions, and Address information and a write signal S5 are generated and applied to the memory circuit 6. The memory circuit 6 uses the output information S2 of the sampling circuit 2 as write data, and data is written in accordance with the address information and the write signal S5. Therefore, the internal information SIO of the information processing device 10 before and after trace stop detection is stored in the memory circuit 6 in an amount equal to the memory capacity of the memory circuit 6. Memory circuit 6
In other words, the internal operation timing of the information processing device 10 can be changed to the memory information S6 by sending the read mode setting information, read signal, and address information S57 from the data processing/control unit 7 to the memory control circuit 5. are sequentially read out, the data is analyzed and displayed on the CR7 display 9. Then, the internal operation timing of the information processing device 10 can be known from the displayed content. In addition, the trigger setting pattern includes a logical AND AND condition consisting of a logic level of 1°0 or By the way, there is a glitch trigger. There is also a pulse width specification function that allows a trigger to be applied only to patterns with a certain width.

[Problem B that the invention attempts to solve]

Conventional logic analyzers are configured as described above, so when a trigger is applied when the input pattern of operation information from the information processing device 10 to be analyzed becomes greater than or less than a specified width, there are inputs that can be specified. The width of the pattern is limited by the sampling period, so
If you want to trigger on an input pattern with a long duration,
If you do not increase the sampling period, you will not be able to specify the required width, which will reduce the resolution of the above operating information and make analysis impossible. Since it cannot be specified, the range of the input pattern of the above-mentioned operation information becomes small, and there are problems such as analysis becomes impossible.This invention was made to solve the above-mentioned problems, and the sampling period and By operating the trigger, regardless of the duration of any input pattern,
An object of the present invention is to obtain a logic analyzer that can perform detailed timing analysis of operating information of an information processing device with high resolution.

[Means for Solving the Problems] A logic analyzer according to the present invention connects a counter between a clock generator, a trigger generator, and a data processing/control section, and performs counter control sent from the data processing/control section. The continuation signal of the input pattern is set by the signal and data information, and the write clock and trace stop signal from the trigger generator 4 are counted up at the clock cycle of the clock generator, and when the set time is reached, the trigger output control signal is output. is sent to the data processing/control section. [Function] The counter in the present invention is configured such that when a request is made to operate a trigger when the input pattern of operation information from the information processing device continues for a certain period of time, the counter reaches a continuation time arbitrarily set by a key operation or the like. Then, a trigger output control signal is sent to the data processing/control unit, which operates to release the write clock and trace stop signal locking the memory control circuit.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 12 is a counter for monitoring the trigger pattern duration, 5712 is a counter control signal and data information obtained by processing setting data from the key operation unit 8 in the data processing/control unit 7, and 5127 is a counter for trigger generator 4. This is a trigger output control signal from the counter that is given to the data processing/control unit 7 for sending and receiving setting information.
Other components that are the same as those shown in FIG. 2 are designated by the same reference numerals, and redundant explanation thereof will be omitted. Next, the operation will be explained. A process will be described when a request is made to operate a trigger when an input pattern of operation information from an information processing device to be analyzed continues for a certain period of time. Address information of the information processing device 10 to be analyzed. data information, control signals, status signals. Operation information S10 such as error information is input to the sampling circuit 2 via the comparator 1 of the logic analyzer LA. On the other hand, among the output signals S1 of the comparator 1, the clock generation signal is input to the clock generator 3, and information processing is performed according to the clock generation conditions set by the clock setting information 337 etc. sent from the data processing/control unit 7 in advance. A clock S3 synchronized with the internal operation of the device 10 is generated and sent to the sampling circuit 2, trigger generator 4, and counter 12. After sampling the output signal 31', this sampling circuit 2 becomes the input data of the memory circuit 6, and a part of the data goes to the trigger generator 4, and trigger trace settings sent in advance from the data processing/control section 7. It is compared with trigger trace conditions such as specific command, specific data, specific address, etc. set by information S47,
A clock including a signal and a trace stop signal S4 are generated, and this is used by the counter 12 and the memory control circuit 5.
is input. In the memory control circuit 5, the write mode, trigger stop, and delay are set according to the write mode, trigger stop, and delay information 357 sent in advance from the data processing/control unit 7, and the write clock and trace stop signal S4 are locked. has been done. The counter 12 performs data processing and
The duration of the input pattern is set by the counter control signal and data information 5712 sent from the control unit 7, and is counted up at the cycle of clock S3 by the write clock and trace stop signal S4 until the set duration is reached. Then, a trigger output control signal 5127 from the counter 12 is sent to the data processing/control section 7. The data processing/control unit 7 uses this trigger output control signal 512
7, the write clock and trace stop signal S4 that had been locked to the memory control circuit 5 are released, and the address counter is counted up every time a write clock is input according to the previously set conditions. Address information and a write signal S5 are generated and applied to the memory circuit 6. 2, by applying a trigger at an arbitrarily set duration of an input pattern, regardless of the sampling period in the sampling circuit 2, timing analysis with high resolution can be performed. Note that the subsequent operation is the same as the conventional one. Note that in the above embodiment, monitoring of the trigger duration time was realized by a hardware configuration using the counter 12, but the function of the counter 12 may be performed by software processing in the data processing/control unit 7. [Effects of the Invention] As described above, according to the present invention, the counter control signal sent from the data processing/control unit by key operation, etc.
The duration of the input pattern is set using the data information, and the duration is counted up by a counter at the clock cycle of the clock generator using the write clock and trace stop signal from the trigger generator.
The configuration is such that when the set time is reached, the trigger output control signal is returned to the data processing/control unit, so a trigger can be applied at any duration of operation information, regardless of the sampling period. This has the effect of shortening the analysis time for phenomena with low reproducibility, and making it possible to perform detailed timing analysis with high resolution.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram showing the configuration of a logic analyzer according to an embodiment of the present invention, and FIG. 2 is a block connection diagram showing the configuration of a conventional logic analyzer. 2 is a sampling circuit, 3 is a clock generator, 4
is a trigger generator, 5 is a memory control circuit,
6 is a memory circuit, 7 is a data processing/control unit, 8 is an operation key, 10 is an information processing device to be analyzed, and 12 is a counter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others)

Claims (1)

[Claims] A sampling circuit that samples operational information of an information processing device to be analyzed, and a clock that is synchronized with the internal operation of the information processing device according to a clock generation signal in the operational information and clock setting information set in advance. a clock generator that inputs to the sampling circuit, a trigger generator that generates a write clock based on the clock from this clock generator, output data of the sampling circuit and trigger trace information set in advance, and a write clock from this trigger generator. A memory control circuit that generates address information and a write signal in accordance with preset write mode, trigger stop, and delay information each time a clock is input, and address information from this memory control circuit.
Internal operation timing data of the information processing device written in the memory circuit by controlling a memory circuit that writes output information of the sampling circuit, the clock generator, the trigger generator, and the memory control circuit according to a write signal. In a logic analyzer equipped with a data processing/control unit that reads and analyzes the data, the duration of the input pattern of the operation information is set by the counter control signal and data information output from the data processing/control unit, and A counter is provided that counts up at the clock cycle of the clock generator using the write clock and trace stop signal from the trigger generator, and sends a trigger output control signal to the data processing/control unit when the set duration time is reached. A logic analyzer featuring