JPH02264324A - Shift circuit - Google Patents

Abstract

PURPOSE:To obtain a correct solution by using a fixed point processor even if difference between the maximum and the minimum values of a signal is large by constituting the shift circuit of input data and the selection circuit of shift quantity under the control of program control. CONSTITUTION:This circuit 10 is connected between a processor and an accumulator. When data whose bit width was expanded by the arithmetic operation of the accumulator is inputted to an input port 1, it is shifted, and is contracted into the bit width of a data bus, and is outputted from an output port 3. This circuit 10 is provided with a shift quantity calculation circuit 12 not using the program control, and a calculates the shift quantity from the input data, and outputs it to a register 18. A shift part 14 shifts data ID inputted from the input port 1 according to the shift quantity S0 given from a multiplexer 16, and outputs the output data OD of this result to the output port 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic circuit, and particularly to a shift circuit applied to an arithmetic circuit that performs fixed-point arithmetic.

(Prior Art) Recently, digital signal processors (DSPs) have been widely used in the field of signal processing.As is well known, digital signal processors can be divided into two types: one based on floating-point arithmetic and the other based on fixed-point arithmetic. There is something that says. Digital signal processors based on floating-point arithmetic express numbers by dividing them into an exponent and a mantissa.
It is characterized by a wide range of numerical values that can be expressed with the same bit width, that is, a wide dynamic range. However, as a result of calculation processing,
When the value of the mantissa deviates from a predetermined range, a normalization process that shifts the value of the mantissa to the left or right and accordingly increases or decreases the exponent by the amount of shift to keep the mantissa within the predetermined range. Therefore, one circuit is complicated, and compared with a digital signal processor based on fixed-point arithmetic, it has disadvantages of slow operation, high cost, and large power consumption.

Digital signal processors based on fixed-point arithmetic express numerical values using only the mantissa part, and the exponent part is fixed. Therefore, although the dynamic range is narrow, it is superior in terms of high speed operation, low price, and low power consumption, and is used in many devices.

Digital signal processors based on fixed-point arithmetic, such as the Texas Instruments Model TMS 32030, incorporate a shift circuit to compensate for the narrow dynamic range. This shift circuit extracts a desired portion of the bit width expanded by calculation processing using an external signal. This signal is given from a program control mechanism that executes a program in which the shift amount is written. . Such a program simulates and evaluates all the signals scheduled for calculation processing, determines the amount of shift that can most effectively utilize the calculation capacity of the calculation section, and
Created.

(Problem to be Solved by the Invention) However, in this method, in a digital fist signal processor, for example, when calculating the signal ratio based on the average signal power from the N-order phase between signals, the signal has a maximum value and a minimum value such as an audio signal. When the signal has a large difference between the two, a first-order problem occurs.

When finding a solution using a digital signal processor based on floating-point arithmetic, the dynamic range of the numerical values that can be expressed is wide, so the problems that arise when using a digital signal processor based on fixed-point arithmetic are However, the digital signal processor itself operates slowly, is expensive, and consumes a lot of power.

On the other hand, when finding a solution using a digital signal processor based on fixed-point arithmetic.

The amount of shift must be defined in the program. Therefore, as mentioned above, simulations and evaluations are performed for all planned signals to determine the amount of shift that can most effectively utilize the computational power of the arithmetic unit. There is the following problem.

For example, if the shift amount is determined according to the signal with the expected maximum value, most of the signals will take a smaller value than necessary, which wastes the calculation power of the arithmetic unit.
Therefore, an accurate solution cannot be obtained. Therefore, if the shift amount is determined according to the expected average value of the signal, when the signal with the maximum value is input, it will exceed the calculation capacity of the arithmetic unit, so overflow will occur. occurs. This results in incorrect results. In other words, no matter how the shift amount is determined, the correct result cannot always be obtained.Using a digital fist signal processor based on floating point arithmetic is expensive and slow. If a digital signal processor based on fixed-point arithmetic is used, it is impossible to determine the shift amount to be written in the program, so a correct solution cannot be obtained.

The present invention eliminates the above-mentioned drawbacks and provides a shift circuit that makes it possible to obtain accurate solutions using a fixed-point based digital signal processor even when the difference between the maximum and minimum values of a signal is large. The purpose is to provide.

(Means for Solving the Problems) According to the present invention, a shift circuit that shifts and outputs input data under program control converts a sign bit following the most significant bit of input data into a single bit. A shift amount calculation means for calculating a first shift amount, and a second shift amount described in the program are input, and a selection device for selecting either the first or second shift amount under program control. and a shifting means that receives input data, shifts the input data according to the selected shift amount, and outputs the shifted data.

(Function) According to the present invention, the first shift amount for converting the sign bit following the most significant bit of input data into 1 bit is determined by the shift amount calculation means.

On the other hand, the 0 selection means to which the second shift amount described in the program is input is under program control, selects one of the two, and inputs it to the shift means. In addition to controlling the shift of the shift means using the first shift amount determined by the program, control is performed using a second shift amount that maximizes the amount of information in response to input data that cannot be executed by program control. Furthermore, by fixing or updating the second shift amount, data corresponding to the calculation can be supplied.

(Example) Next, an example of a shift circuit according to the present invention will be described in detail with reference to the accompanying drawings.

In the shift circuit 10 of the embodiment of the present invention shown in FIG.
When data whose bit width has been expanded by the operation of the accumulator is input to the input port 1, this arithmetic circuit shifts the data to reduce it to the bit width of the data bus, and outputs it to the data bus from the output port 3. Shifting is controlled by control signals from a program control section (not shown) of the digital fist signal processor. This point is
This is basically the same as the conventional example.

However, one fundamental difference between the present embodiment and the conventional example is that it includes a shift amount calculation circuit 12 and can perform shift control not based on program control.

This circuit 10 has a shift section 14, which transfers input data In input from an input port l to a multiplexer 01.
This circuit shifts according to the shift amount SO given from 0X) 113 and outputs the resulting output data OD to the output port 3. The shift amount calculation unit 12 is an arithmetic circuit that calculates a data shift amount S1 from the input data 10 from the input port 1 and outputs this from its output 20 to the register 18. From the program control section of the digital fist signal processor.

A register control signal S4 is input to the control signal input terminal 5 of the register 18, and a program shift amount S2 and a selection signal S3 are input to input terminals 7 and 8 of the multiplexer 16, respectively.

The register 18 is a circuit that fixes or updates the data shift amount held by the register control signal S4 according to the operation mode described later, and provides the data shift amount S5 to the multiplexer 1B. The multiplexer 1B selects the first shift amount S5 from the register 18 or the second shift amount S2 from the program control unit in accordance with the selection signal S3 applied to the control terminal 8, and selects the first shift amount S5 from the register 18 or the second shift amount S2 from the program control unit as the final shift amount SO. This is a circuit that supplies the signal to the shift section 14.

FIG. 2 shows a specific example of the circuit configuration of the shift amount calculating section 12.
When inputted, a shift amount is calculated and a shift amount S1 indicating the calculation result is output to the output port 20. In this example, the input data ID is 8 bits NSR, a8.
It consists of a5 to aO, and the output data Sl indicating the shift amount is 7 bits) bo, blNbEl.

Between both ports l and 20, an exclusive OR gate 31,
32-37, OR game) 41.42-45, and two-man AND game where one input is negative logic) 51.52-5B
are connected and configured as shown in the figure. This circuit 1
2, for example, an input bit string r is input to input port 1.
When 0OIOQ100J is input, output port 20
The bit string r0100000 is used as the shift amount Stl.
J is generated. This will be referred to here as example (a). For example, when an input bit string rllll0IIOIJ is input, an output bit string r0010000J is generated. This is taken as example (b).

Since the sign bit following MSH in the input bit string, ``0'' in example (a) and ``ril'' in example (b), is not a significant bit, the shift amount calculation unit 12 uses the shift unit 14 to select a plurality of sign bits. A first shift amount St for conversion into a single bit is generated. As a result, the shift unit 14 performs a 1-bit shift for example (a) and a 2-bit shift for example (b). Therefore, compared to the conventional shift method, the number of effective digits of the output data On obtained at the output 3 of the shift section 14 increases, and the amount of information thereof increases.

This shift circuit IO has three operation modes such as primary. First of all, the program control section registers 18
A register control signal S4 instructing to fix the register value held by the person is given to the multiplexer 18, a second shift (11S2) is given to the person's cuff, and a second shift amount S2 is given to the control human power 8. This is a case where a selection signal S3 instructing selection is given. In response to this selection signal S3, the multiplexer 18 selects the second shift amount S2 and outputs it to the shift unit 14 as the final shift amount SO. In this case, the actual shift amount SO is S2 given by the program control section, and therefore the shift is performed under program control as in the conventional case.

In the second mode of operation, the program control section registers 1
8, a new first shift amount St is sent from the shift amount calculation unit 12.
Gives a register control signal S4 instructing to take in the
The multiplexer 1B is given a selection signal S3 that instructs the human power 8 to select the first shift amount S5. The shift amount calculation section 12 takes in the input data In using the above-mentioned function, and in response to the 0 selectivity signal S3 for calculating the shift amount, the multiplexer 1B selects the first shift amount S1 and selects the first shift amount S1. The updated shift amount SO is provided to the shift unit 14.

In the third operation mode, the program control unit sends a register control signal S to fix a register value in the register 18.
4, and multiplexer 1B has the first
In response to the 0 selectivity signal S3 that provides the selection signal S3 instructing selection of the shift amount S5, the multiplexer 18 selects the first shift amount S5 held in the register and shifts this as the shift amount SO. Send to Department 14.

By combining the second and third operation modes realized in this embodiment, the problem of finding the ratio between signals can be solved even if the signal has a large difference between the maximum value and the minimum value, such as an audio signal. In some cases, a fixed-point based digital signal processor can provide an accurate solution. In addition, we will use a concrete example to demonstrate that by combining the first, second, and third operating modes, accurate solutions can be obtained using fixed-point based digital signal processors in the above-mentioned cases. and explain.

When calculating the ratio of the 0th-order and 1st-order correlation values of signals, the equation of the j-order correlation value Cj of m input signals is expressed as follows. However, Si is the first input signal, and the ratio of 0th-order to 1st-order correlation values is expressed as C1/Co.

Here, the external data width is 8 bits) (-128 to ÷127
s-4゜aO-
58,51m14G, 52-72.53m-80,5
4m4B, the signal input to the shift circuit 10 is C0=6400. CI=1280 is calculated.

In conventional shift circuits, the shift amount is written in the program. For example, if the output of such a shift circuit is 8
If it is written as "shift 6 bits to the right" to fit within the bit width, then CG=100. C.I.
=20, and it is calculated as CI/C0·2G/100.

When this is done in the shift circuit IO in this embodiment, C
When O is input, the first shift amount S5 is determined by the input data ID, and the shift section 14 shifts the data to the right by 6 bits so that the width is within 8 bits. As a result, C0=10
When the value becomes 0 and the primary CI shift is applied, the shift operation similarly shifts 6 bits to the right. Therefore, CI=20. From this result, CI/C0=20/100 is calculated.

Next, run this same program with the input signal size l/
Consider the case where the number becomes 8. This corresponds to when the signal is small, and the correct answer is CI/C0=20/100.

In a digital signal processor based on fixed-point arithmetic in which the amount of shift is determined by the program, the shift is not performed to the right by 6 bits as in the previous operation, so the output of the shift circuit is CO=1. CI=0, and the calculation is CI/CO=0/I, and the correct solution cannot be found.

However, in the shift circuit 10 of this embodiment, when data CO is input, the first shift amount is updated with input data ``0''. That is, since the input value is within the 8-bit width, the second operation mode is entered in which no shifting is performed. The output of the shift circuit 10 becomes co=too, and when the primary Ct is input, the shift operation is not performed according to the information in the register I8.

Therefore, the output of the shift circuit IO becomes CI=20, which is calculated as C1/C0·20/100.

(Effects of the Invention) As described above, according to the present invention, the shift circuit compresses the sign bit that does not have a significant value into one bit.
The information amount of the shifted data increases, allowing other processing circuits to perform accurate calculations. In addition, in signal processors that calculate signal ratios using fixed-point arithmetic, if the shift amount was determined only by a program as in the conventional example, incorrect solutions would be generated if changes in input data could not be followed. In the invention, it is possible to perform a shift corresponding to input data, and an incorrect solution will not be output due to the shift.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a shift circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of the circuit configuration of a shift amount calculating section in the embodiment shown in FIG. , 1/1 10, , Shift circuit 12, , Shift amount calculation unit 14, , Multiplexer 18, , Register

Claims (1)

[Claims] 1. A shift circuit for shifting input data and outputting the same under program control, the circuit comprising a first shift circuit for converting a sign bit following the most significant bit of the input data into a single bit. a shift amount calculation means for calculating the first shift amount; and a selection means for receiving the second shift amount described in the program and selecting either the first or second shift amount under program control. , a shift circuit that receives the input data, shifts the input data according to the selected shift amount, and outputs the shifted data. 2. The shift circuit according to claim 1, wherein the circuit includes storage means for storing the determined first shift amount, and the storage means selects fixing and updating of the storage contents of the storage means. A shift circuit characterized in that it operates under program control.