JPH02264579A - Driving method for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent the degradation of picture quality by increasing the maximum absolute value of level of the clock signal applied in a period when a CCD area stores the signal charge compared with the maximum absolute value of level of the clock signal applied in a frame transfer period. CONSTITUTION:The signals phiP1, phiP2 and phiP3 are applied to the gate electrode 3 of an image pickup CCD areas A via the terminals 5, 6 and 7. Simultaneously, the clock signals phiS1, phiS2 and phiS3 are applied to the gate electrode 3 of storage CCD area B via the terminals 8, 9 and 10. The maximum absolute value of the level of the clock signal applied in the period when the area A stores the signal charge is set larger than the maximum absolute value of the level of the clock signal applied in a frame transfer FT period when the electric charge is transferred to the area B from the area A. Therefore the level of the clock signal which is applied to the terminal 5 in a charge storing period is set at 'HH' higher than the conventional 'H'. Thus the width of the depletion layer spreading into a substrate 1 is proportional to 1/2 square of applied voltage in the abrupt junction approximation. Consequently, the smear ratio is extremely reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for driving a frame transfer (hereinafter abbreviated as "FT") type solid-state image sensor, and in particular, to a method for driving a solid-state image sensor using a frame transfer (hereinafter abbreviated as "FT") method, and particularly to a method for suppressing smear (image blurring). It is about the method.

[Prior Art] FIG. 2A is a schematic diagram showing an example of a cross-sectional structure of an FT type solid-state image sensor. In this figure, a thin dielectric film 2 is formed on a p-type semiconductor substrate 1, for example. On the dielectric film 2, a plurality of gate electrodes 3 for configuring a CCD (charge-coupled device) arranged vertically within the light-receiving surface and a plurality of gate electrodes 11 for configuring a CCD arranged horizontally. is formed. Since the gate electrodes 11 are arranged in a direction perpendicular to the plane of the drawing, only one gate electrode 11 is shown.

The range indicated by arrow A in the figure indicates the imaging CCD area,
The area indicated by arrow B is the storage CCD area, and the area indicated by arrow C is the horizontal CCD area for transferring charges in the direction perpendicular to the plane of the paper.
It shows the area. A light shielding film 4 is formed on the storage CCD area B and the horizontal CCD area C to prevent light from entering.

That is, this solid-state imaging device receives incident light from the gate electrode 3 side, and the gate electrode 3 is formed of a light-transmitting conductive material, such as polysilicon.

Clock signals φP++ and φP2+ are applied to the gate electrode 3 of the imaging CCD area A via terminals 5°6.7, respectively.
φP, and the gate electrode 3 of the storage CCD region B is provided with a terminal 8. 9. 10 respectively via clock signals φ84. φ, 2. φ8. is given. That is, this solid-state image sensor is of a three-phase drive type, and the number of vertical pixels is two.

A clock signal φH is applied to the gate electrode 11 of the horizontal CCD area C via a terminal 12.

FIG. 3 shows conventional clock signals φP, .about.φP3+φ6. ~
φ3. FIG.

FIG. 2B shows the potential distribution within the semiconductor substrate 1 at time t1 in FIG. 3, corresponding to FIG. 2A.

The range indicated by arrows T and τ in FIG. 3 represents the charge accumulation period, and the period indicated by the arrow TFT is the frame transfer (F
T) represents a period.

During the charge accumulation period TST, the clock signal φP is set to H (high) level in the imaging CCD area A, and the clock signal φP2+φP is set to L (low) level.

Therefore, as seen in FIG. 2B, the position W1. in the semiconductor substrate 1 below the gate 11 pole 3 to which the clock signal φPl is applied In W2, the depletion layer expands and a potential well is formed. Electrons generated by the incident light are stored in these potential wells and become signal charges. This signal charge ff1Qs+c+ is proportional to the light intensity I, the accumulation time T, T, and the width W of the depletion layer, and is expressed by the following equation (1).

Qs+ G-klT5vW = (1
) Here, k is a proportionality constant determined by the light transmittance of the gate electrode 3, etc.

When the accumulation period TST ends and the FT period TFT begins, the clock signal applied to the imaging CCD area A and the storage CCD area B becomes a transfer waveform, and the signal charges accumulated in the imaging CCD area A are transferred to the storage CCD that is shielded from light. Transferred within area B at high speed. In this FT period TFT, the potential well moves to the right in FIGS. 2A and 2B, so for example, even if light is incident only at position W2 in FIG. 2B, the potential well at position W1 is W2
receives light irradiation when passing through. Therefore, false signal charges Qsn are generated in the potential well where no signal charges should actually exist.

This phenomenon is called smear, and when viewed on a playback screen, it looks like white streaks are occurring above and below the light irradiation area, and it significantly deteriorates the image quality. This false signal charge QSM is expressed by the following equation (2) similarly to equation (1).

Qs M −k I TF t W ... (2
) The ratio of the false signal charge Qsr+ to the signal charge Qs r a is called the smear ratio R8M, and is expressed by the following equation (3).

Rg gate "Qs bar/Qs+G mk ITF t W/k I T57 W"=Tpv
/Tg7...(3) The signal charges transferred to the accumulation CCD area B are transferred to the horizontal CCD area C one by one as vertical pixels while the imaging CCD area A enters the next accumulation period T, T. It will be done. The horizontal CCD area C, which has received the signal charges for one stage, is connected to the output section (not shown) provided at the end extending in the direction perpendicular to the paper surface of FIG. 2A before the signal charges for the next stage are transferred. ). The clock signal φ8 applied to the horizontal CCD area C is well known and is not directly related to the features of the present invention, so its explanation will be omitted.

[Problems to be Solved by the Invention] In the conventional driving method of an FT solid-state image sensor, F is reduced in order to reduce the smear ratio R5M shown in equation (3)
It is known to make the T period TFT shorter than the storage period TsT. For this purpose, the vertical CCD areas A and B must be driven at high speed in this FT period TFT. However, in general, the gate electrode capacitance of vertical CCD regions A and B is several thousand pF or more, and due to problems such as a decrease in transfer efficiency and charge transfer capacity due to the blunting of the clock signal waveform, the frequency of the tarock signal in the FT period TPT (FT
There was a limit to how high the frequency could be raised.

In view of such problems in the prior art, an object of the present invention is to use the same FT frequency as the conventional one (even with a smear ratio R5 of 1).
An object of the present invention is to provide a method for driving an FT solid-state image sensor that can improve M.

[Means for Solving the Problems] A method for driving a solid-state imaging device according to the present invention includes an imaging C for accumulating signal charges generated by light incidence for a predetermined period.
In a so-called frame transfer type solid-state imaging device that includes a CD area and a storage CCD area that is provided adjacent to the CD area and is shielded from light, a clock is applied during a period when the imaging CCD area is accumulating signal charges. The maximum absolute value of the signal level is set to be higher than the maximum absolute value of the clock signal level applied during the so-called frame transfer period in which charge is transferred from the imaging CCD area to the storage CCD area. It is a feature.

[Function] In the driving method of the solid-state image sensor according to the present invention, (in the island, the largest absolute value of the clock signal level during the charge accumulation period is larger than that during the FT period, so the depletion layer during the charge accumulation period is The width wsT becomes larger than the width WF□ of the depletion layer during the FT period.

That is, the smear ratio R expressed by equation (3).

. is expressed as the following equation (4), and becomes smaller by the ratio shown by WFT/WsT.

RsrI-kITFTWF 7 /k ITS 7WB
y= TF T WF v / T s t Ws
T (4) [Example] FIG. 1 is a timing chart showing a clock signal used in a method for driving a solid-state image sensor according to an example of the present invention. FIG. 1 is similar to FIG. 3, except that the clock signal φP applied to the terminal 5 during the charge accumulation period T,
The level is set to the HH level, which is higher than the conventional H level.

The width of the depletion layer spreading in the semiconductor substrate 1 is proportional to the 1/2 power of the applied voltage under the step junction approximation.

Therefore, for example, when the H level is 5V and the HH level is 1V,
In the case of 5V, if the smear ratio RSM is calculated according to equation (4), the following equation (5) is obtained.

Rs M -TF T J 5/Ts T J 15-
〇, 58TF T /Ts T...(5
) That is, the smear ratio R8 of this embodiment is reduced to only 58% of the smear ratio R8 of the conventional method using the same FT frequency.

By the way, the clock signal φP, ~φ during the FT period TFT
The accumulated CC is not related to the level of P or the smear ratio RsM.
D area B clock signals φs1 to φ5. Since the level is exactly the same as before, problems such as deterioration of transfer efficiency do not occur.

In the above embodiments, the case where electrons serve as signal charges has been described, but it will be understood that the present invention can also be applied to cases where holes are used as signal charges. In this case, the polarity of the voltage applied to the gate electrode may be reversed.

Further, although three-phase drive has been described as an example of a CCD driving method, it is clear that two-phase drive or four-phase drive can also be used.

Further, although the FT type solid-state imaging device has been described using a type in which light enters from the front surface, it is clear that the present invention can also be applied to a type solid-state imaging device that receives light from the back side of the substrate.

[Effects of the Invention] As described above, according to the present invention, the amplitude of the clock signal in the imaging CCD region is larger in the charge accumulation period than in the FT cut-off period, so it is possible to use the same FT frequency as in the conventional case. However, the smear ratio can be reduced. In other words, it is possible to provide a method for driving a solid-state image sensor with less deterioration in image quality due to smear.

[Brief explanation of drawings]

FIG. 1 is a timing chart showing clock signals used in a method for driving a solid-state image sensor according to an embodiment of the present invention. FIG. 2A is a schematic diagram showing the cross-sectional structure of the FT solid-state image sensor. FIG. 2B is a diagram showing a potential distribution corresponding to FIG. 2A. FIG. 3 is a timing chart showing clock signals used in a conventional method for driving a solid-state image sensor. In the figure, φ-7 to φP are clock signals applied to the imaging CCD area A, φ3. .about.φ,3 is a clock signal applied to the storage CCD area B, T, is the storage period, and TFT is the frame transfer period. In each figure, the same reference numerals indicate the same contents or corresponding parts.

Claims (1)

[Scope of Claims] A so-called frame transfer system including an imaging CCD area for accumulating signal charges generated by light incidence for a predetermined period, and an accumulation CCD area provided adjacent to the imaging CCD area and shielded from light. In the solid-state imaging device of the above-mentioned method, the one having the largest absolute value of the clock signal level applied during the period when the imaging CCD area is accumulating signal charges transfers the charge from the imaging CCD area to the storage CCD area. A method for driving a solid-state image sensor, characterized in that the level of a clock signal applied during a so-called frame transfer period is set to be higher than the largest absolute value.