JPH02265092A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To execute a low noise and high speed operation by constituting an output buffer of a series connecting circuit of a parallel circuit of a first PchFET and an NchFET, and a second PchFET, and controlling a first PchFET by a signal of an output level deciding circuit. CONSTITUTION:A voltage setting circuit 30 sets a reference voltage by a resistance 31 and NchFETs 32, 33, and a level deciding circuit 34 compares a reference level with an output level l and constituted of a current mirror. When a signal (e) of an output buffer 20 is varied to 'H', a signal (n) of the deciding circuit 34 is 'L' until VR, and a PchFET 35 is turned on and becomes 'H' at a high speed. When it reaches VR, the FET 35 is turned off and only an NchFET 36 is turned on and the signal (e) rises slowly up to (VCC-Vth). A noise generated at the time when the signal (e) is varied to 'L' is relaxed, comparing with the case of conventional VCC since the 'H' level is (VCC-Vth).

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an output buffer circuit for a semiconductor memory device, and particularly to an output buffer circuit that can reduce noise generated during data output and can operate at high speed. It is related to circuits. , [Prior Art] FIG. 5 is a block diagram showing the configuration of an output buffer circuit of a conventional semiconductor memory device. In the figure, (10) is a pre-output buffer circuit that receives the signal a from the sense amplifier (1) and the signal S from the output control circuit (2). It consists of two NOT circuits (1) and (14).(2
0) is the signal c-d from the pre-output buffer circuit (10)
It is an output buffer circuit that inputs P channel MO
It is composed of an S transistor (21) and an N channel MOS transistor (24). (3) is a data output terminal, and a current i flows through the 1 and N channel MOS transistor (24) which outputs the signal e from the output buffer circuit (20).

FIG. 7 is a block diagram showing another configuration of a conventional output buffer circuit. In Figure 7, (1) to (3) - (1
(11 to (141-t20) and (24) are the same as those shown in FIG. 5, so their explanations are omitted. The difference from FIG. 5 is that in the output buffer circuit (20) - signal The only difference is that the circuit that inputs the information is composed of a NOT circuit (22) and an N-channel MOS transistor (23).

Next, the operation will be explained.

In the output buffer circuit (20) of FIG. 5, when the signal is at the H level, the output of the NOR circuit 111) is
goes to L" level, and the output C of the next stage NOT circuit (12)
becomes H level. When the signal C is at the M level, the P-channel MO8) transistor (2+) is turned off. When the signal d is at the L level, the N-channel MOS transistor (24) is turned off. Therefore, when the signal e is at H level, the signal e is not output. Next, the signal C is at H level, and the signal d is also at F (level - N channel MOS transistor t24).
Only transistor (21) is ONL, H level signal e
Output.

A current i flowing from the data output terminal (3) to the ground flows through the N-channel MOS transistor (24J).f$6 Figure is a timing chart showing each signal of the circuit in Figure 5.The current i flows when the signal e changes. It reaches a maximum instantaneously and then gradually decreases.The instantaneous increase in current 1 causes the leakage ground level to fluctuate and generate noise.

In the output buffer circuit (20), P is applied to the load transistor.
Channel MOS noise increases. Further, the operation of the circuit shown in FIG. 7 is the same as that of the circuit shown in FIG.

In the output buffer circuit (20) in FIG. 7, the N-channel MOS transistor 123) is used as the load transistor, so the -H level becomes Vcc-Vth.
There is a problem that the level of noise generated when the signal changes to H level is insufficient, and that the operation becomes slow when the signal e changes from L level to H level.

FIG. 8 is a timing chart showing each signal in the circuit of FIG. 7, and shows the situation described in item 1.

[Problem to be solved by the invention]

Conventional output buffer circuits are configured as described above, so using a P-channel MOS transistor as a load transistor results in high-speed operation but increases output noise, and using an N-channel MOS transistor as a load transistor causes problems. Although this reduces the output noise, there is a problem that high-speed operation cannot be achieved.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an output buffer circuit with low output noise and capable of high-speed operation.

[Means for Solving the Problems] The output buffer circuit according to the present invention includes a load transistor portion including a parallel circuit of a first P-channel MOS transistor and an N-channel MOS transistor, and a second P-channel MOS transistor. In addition to the circuits connected in series, an output level determination circuit is also provided, and a circuit is provided in which the first P-channel MOS transistor is turned off by a signal output from the determination circuit.

[Effect]

In this invention, the output of the output level determination circuit
A parallel circuit of a first P-channel MOS transistor and an N-channel MOS transistor that turn OFF and a second P-channel MO let

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an output buffer circuit of a semiconductor memory device. In the figure, (1) to (3) - (10 to (
14), (20), (21), (2nd place is the same as that shown in the conventional example of FIG. 5, so the explanation is omitted. The points different from the circuit of FIG. 5 are shown below. (30) ) is the output buffer circuit, which is a P-channel MO8) transistor, (43) to (4
5) is an N-channel MOS transistor. FIG. 3 is a timing chart showing each signal in the circuit of FIG. 1.

Next, the operation will be explained. Pre-output 8777 circuit (1
The basic operations of the pre-output buffer circuit (1, 0) and the output buffer circuit (20) shown in the conventional example in FIG.
1. Same as output buffer circuit (20). FIG. 3 shows a voltage setting circuit, which is constructed as follows.

A resistor f31) and two N-channel MOS transistors (331 is a circuit for setting a reference voltage for determining the output level. 134) receives the output level signal l and the reference voltage signal m as inputs. This is an output level determination circuit, for example, composed of a current mirror as shown in the circuit diagram of FIG. (35) is the output level judgment circuit (
This is a P-channel MOS transistor that inputs the signal n from the circle to its gate. (The column is an N-channel MOS transistor for supplying voltage to the output buffer circuit (20). In the case of (41) and (42) in FIG. Tame-P
Channel MO8) becomes a crystal. When the level of the output signal e reaches VR - After the P-channel MOS transistor C (5) is turned off, the N-channel MOS transistor (only 30 is ONL) - The signal e becomes Vcc.
-Vth level is relaxed compared to the case (conventional).

When the current mirror shown in FIG. 2 is used in the output level determination circuit (34), it stops operating when Vcc becomes low. The level of signal n at this time is determined by the P/N ratio of the current mirror. Normally, the P/N ratio is set to 1/2 or lower, so the signal n goes to L level below 1/2VCC, and the P channel MO5) transistor turns on.In other words, when Vcc becomes low to a certain extent, the output becomes Vcc. However, if Vcc is high, the output will be Vcc −
It becomes up to Vth. When Vcc changes, it changes rapidly to the level of VR.

In the above embodiment, the case where the signal l is supplied from the signal f has been described, but it may also be supplied from the signal e.

FIG. 4 is a circuit diagram showing an output/-, a buffer circuit according to another embodiment of the present invention. In the figure (1) to (3)
-(10)~(14), C2ω, +21+-041-!
30) to (The multiplication is the same as that shown in FIG. 1, so the explanation will be omitted. Signal 1 is supplied from signal e, and has the same effect as the above embodiment.

Further, in the above embodiment, in the circuit for setting VR, N
Although the channel MOS transistors (32) and C33) are configured in two stages, they may be configured in one stage or three or more stages, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the output buffer circuit according to the present invention, the load transistor portion of a conventional output buffer circuit is replaced with a first P-channel MOS transistor and an N-channel MOS transistor.
Parallel circuit with OS transistor and second P-channel MO
Since the circuit is connected in series with the S transistor and an output level judgment circuit is added to control the ON/OFF state of the first P-channel MOS transistor, when -Vcc is high, the output level becomes Vcc -Vth, and the output Effect of reducing noise - When Vcc is low, the output level reaches Vcc, so there is an effect that malfunctions occur quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an output sofa circuit of a semiconductor memory device according to an embodiment of the present invention; FIG. 2 is a circuit diagram showing an embodiment of the output level determination circuit of the circuit of FIG. 1;
The figure is a timing chart showing each signal of the circuit in Figure 1.
FIG. 4 is a circuit diagram showing an output buffer circuit of a semiconductor memory device according to another embodiment of the present invention. FIG. 5 is a block diagram showing an example of an output buffer circuit of a conventional semiconductor memory device.
FIG. 6 is a timing chart showing each signal of the circuit in FIG. 5. FIG. 7 is a block diagram showing another example of the output buffer circuit of a conventional semiconductor memory device. FIG. 8 is a timing chart showing each signal of the circuit in FIG. FIG. In the figure, (1) is a sense amplifier, (2) is an output control circuit, (3) is a data output terminal, l+0+ is a pre-output buffer circuit, (11) is a NOR circuit, (1 is a NOT circuit, and (1) is a NOT circuit. , (13) is a NAND circuit, (20) is an output buffer circuit -(21) -(35)-f41), (4
Thirst is P channel MO5) Run sister +24) -(3
(33), (36), (43), f44) + (
45) is an N-channel MOS transistor, (30) is '
H" level voltage setting circuit - (31) is a resistor - (34) is an output level judgment circuit.
This is the current flowing through the transistor (24). In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A second P-channel MOS transistor is connected to a circuit in which a first P-channel MOS transistor and a first N-channel MOS transistor are connected in parallel between the output terminal of the semiconductor memory device and the first power supply wiring.
The circuit includes a circuit in which channel MOS transistors are connected in series, and a second N circuit is provided between the output terminal and the second power supply wiring.
In an output buffer circuit comprising a channel MOS transistor, and further comprising a circuit for generating a certain reference voltage and an output level determination circuit for comparing the voltage at the output terminal with the reference voltage, the voltage at the output terminal is A signal controlled by ON/OFF of the second P-channel MOS transistor and the second N-channel MOS transistor and output from the output level determination circuit is input to the gate of the first P-channel MOS transistor, ON/OFF of first P-channel MOS transistor
An output buffer circuit characterized by controlling.