JPH02265247A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02265247A JPH02265247A JP1087512A JP8751289A JPH02265247A JP H02265247 A JPH02265247 A JP H02265247A JP 1087512 A JP1087512 A JP 1087512A JP 8751289 A JP8751289 A JP 8751289A JP H02265247 A JPH02265247 A JP H02265247A
- Authority
- JP
- Japan
- Prior art keywords
- region
- base
- conductivity type
- base region
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にバイポーラ型シリコン
・トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to bipolar silicon transistors.
従来、バイポーラ型シリコン・トランジスタは第３図に
示すようにｎ＋型の埋込コレクタ領域２上に形成された
ｎ型のエピタキシャル成長層３ａ中にｎ型のベース領域
１２と電極引出し用の多結晶シリコン膜９ａ、９ｂと接
続する補償ベース領域１１ａ、ｌｌｂが形成され高濃度
の補償ベース領域１１ａ、ｌｌｂと埋込コレクタ領域２
とがエピタキシャル成長層３ａを介して対向する構造と
なっていた。Conventionally, a bipolar silicon transistor includes an n-type base region 12 and polycrystalline silicon for electrode extraction in an n-type epitaxial growth layer 3a formed on an n+ type buried collector region 2, as shown in FIG. Compensation base regions 11a, llb connected to films 9a, 9b are formed, and high concentration compensation base regions 11a, llb and buried collector region 2 are formed.
had a structure in which they faced each other with the epitaxial growth layer 3a interposed therebetween.
上述した従来の半導体装置は補償ベース領域１１ａ、Ｉ
ｌｂとコレクタ領域とが直接接する形状となっていた。The conventional semiconductor device described above has compensation base regions 11a, I
lb and the collector region were in direct contact with each other.
このため高濃度の補償ベースと埋込コレクタ領域とが近
接しているのでベース抵抗の低減のため補償ベース領域
の濃度を高めると、コレクタ・ベース容量の増加、コレ
クタ・ベース耐圧の低下といった素子特性上の問題点が
生じていた。また素子の高速化のため、エピタキシャル
成長領域を薄くし埋込コレクタ領域２と補償ベース領域
の距離を近づけるとやはりコレクタ・ベース容量の増加
を生じるという欠点がある。For this reason, the highly doped compensation base and buried collector region are close to each other, so if the concentration of the compensated base region is increased to reduce base resistance, device characteristics such as an increase in collector-base capacitance and a decrease in collector-base breakdown voltage The above problem occurred. Further, in order to increase the speed of the device, if the epitaxial growth region is made thinner and the distance between the buried collector region 2 and the compensation base region is reduced, there is still a drawback that the collector-base capacitance increases.
本発明の半導体装置は、シリコン半導体基板上に形成さ
れた第１導電型の埋込コレクタ領域、前記埋込コレクタ
領域上に形成された第１導電型のエピタキシャル成長層
、前記エピタキシャル成長層中に形成された第２導電型
のベース領域、前記エピタキシャル成長層中に形成され
前記ベース領域と連結した第２導電型の補償ベース領域
及び前記ベース領域中に形成された第１導電型のエミッ
タ領域よりなるバイポーラトランジスタにおいて、前記
補償ベース領域と前記埋込コレクタ領域の間に絶縁膜を
有し、前記補償ベース領域が前記ベース領域及び前記エ
ピタキシャル領域を介して前記埋込コレクタ領域と接続
されているというものである。A semiconductor device of the present invention includes a buried collector region of a first conductivity type formed on a silicon semiconductor substrate, an epitaxial growth layer of a first conductivity type formed on the buried collector region, and an epitaxial growth layer of a first conductivity type formed in the epitaxial growth layer. a bipolar transistor comprising a base region of a second conductivity type, a compensation base region of a second conductivity type formed in the epitaxial growth layer and connected to the base region, and an emitter region of a first conductivity type formed in the base region. An insulating film is provided between the compensation base region and the buried collector region, and the compensation base region is connected to the buried collector region via the base region and the epitaxial region. .
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す半導体チップの断面図
である。FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.
第３図の従来例との相違点は補償ベース領域１１ａ、ｌ
ｌｂとｎ＋型の埋込コレクタ領域２との間に酸素イオン
注入領域８ａ、８ｂ （酸素イオンを注入し、熱処理に
よりシリコンと反応させて絶縁物にした領域）が存在し
ていることである。The difference from the conventional example in FIG. 3 is that the compensation base regions 11a, l
Oxygen ion implantation regions 8a and 8b (regions into which oxygen ions are implanted and reacted with silicon through heat treatment to become an insulator) are present between lb and the n+ type buried collector region 2.
次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
第２図（ａ）〜（ｆ）は本発明の実施例の製造方法を説
明するための工程順に配置した半導体チップの断面図で
ある。FIGS. 2(a) to 2(f) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the embodiment of the present invention.
第２図（ａ）に示すように、ｐ型のシリコン基板１中に
選択的にヒ素原子を添加しｎ＋型の埋込コレクタ領域２
を形成した後、エピタキシャル成長法により１μｍ厚に
ｎ型のエピタキシャル成長層３を形成しロコス法などの
選択酸化を素子分離領域に行い１μｍ厚の酸化シリコン
膜４ａ。As shown in FIG. 2(a), arsenic atoms are selectively doped into a p-type silicon substrate 1 to form an n+ type buried collector region 2.
After forming, an n-type epitaxial growth layer 3 with a thickness of 1 μm is formed by an epitaxial growth method, and selective oxidation such as the Locos method is performed on the element isolation region to form a silicon oxide film 4a with a thickness of 1 μm.
４ｂ、４ｃを形成し、５０ｎｍ厚の酸化シリコン膜５．
２００ｎｍ厚の窒化シリコン膜６．５００ｎｍＦＪの酸
化シリコン膜７を順次形成する。次いで、第２図（ｂ）
に示すように、写真蝕刻法により酸化シリコン膜７．窒
化シリコン膜６．酸化シリコン膜５を異方性蝕刻し酸素
イオンを図のように埋込コレクタ層２．エピタキシャル
成長層３ｂの境界領域・にイオン注入し酸素イオン注入
領域８ａ、８ｂを形成する。4b and 4c are formed, and a 50 nm thick silicon oxide film 5.
A silicon nitride film 6 with a thickness of 200 nm and a silicon oxide film 7 with a thickness of 500 nm FJ are successively formed. Next, Fig. 2(b)
As shown in FIG. 7, a silicon oxide film 7. is formed by photolithography. Silicon nitride film6. The silicon oxide film 5 is anisotropically etched to form oxygen ions into the buried collector layer 2 as shown in the figure. Ions are implanted into the boundary region of the epitaxial growth layer 3b to form oxygen ion implantation regions 8a and 8b.
次に第２図（ｃ）に示すように、コレクタ引出し領域と
なる部分の酸化シリコン膜７ｂ、窒化シリコン膜６ｂ、
酸化シリコン膜５ａを除去した後、多結晶シリコン膜９
をＣＶＤ法により３００ｎｍ厚に堆積しレジストを塗布
した後エッチバックを施し図のように多結晶シリコン膜
９が露出するようにレジスト膜１７ａ、１７ｂを残し、
次に、第２図（ｄ）に示すように、露出した多結晶シリ
コン膜を部分的に蝕刻し、次に酸化シリコン膜７ａを除
去する。Next, as shown in FIG. 2(c), the silicon oxide film 7b, the silicon nitride film 6b,
After removing the silicon oxide film 5a, the polycrystalline silicon film 9 is removed.
was deposited to a thickness of 300 nm by the CVD method, a resist was applied, and then etched back to leave the resist films 17a and 17b so that the polycrystalline silicon film 9 was exposed as shown in the figure.
Next, as shown in FIG. 2(d), the exposed polycrystalline silicon film is partially etched, and then the silicon oxide film 7a is removed.
次に、第２図（ｅ）に示すように、多結晶シリコン膜９
を写真蝕刻法により選択的に蝕刻し、ベース引出用の多
結晶シリコン膜９ａ、９ｂにボロン原子をイオン注入法
によって選択的に添加し、コレクタ引出用の多結晶シリ
コン膜９ｃにリンをイオン注入法によって選択的に添加
した後、Ｈ２と０２の混合ガス中で熱酸化を施し酸化シ
リコンＭ１０ａ、１０ｂを２００ｎｍ厚に形成する。こ
のときにｐ型の多結晶シリコン膜９ａ、９ｂよりエピタ
キシャル成長層３ａ中にボロン原子が拡散され補償ベー
ス領域１１ａ、ｌｌｂが形成される。Next, as shown in FIG. 2(e), a polycrystalline silicon film 9
is selectively etched by photolithography, boron atoms are selectively added to polycrystalline silicon films 9a and 9b for base extraction by ion implantation, and phosphorous is ion-implanted to polycrystalline silicon film 9c for collector extraction. After selective addition by a method, thermal oxidation is performed in a mixed gas of H2 and 02 to form silicon oxides M10a and 10b with a thickness of 200 nm. At this time, boron atoms are diffused into the epitaxial growth layer 3a from the p-type polycrystalline silicon films 9a, 9b to form compensation base regions 11a, llb.
次に第２図（ｆ）に示すように、窒化シリコン膜６ａ及
び酸化シリコン膜５ａを除去し開孔を設け、イオン注入
法によりボロン原子をイオン注入しベース、領域１２を
形成した後、ＣＶＤ法で酸化シリコン膜を３００ｎｍ厚
に堆積し異方性蝕刻法により酸化シリコン膜を蝕刻し開
孔の側壁に酸化シリコン膜１３ａ、１３ｂを残す。Next, as shown in FIG. 2(f), the silicon nitride film 6a and the silicon oxide film 5a are removed, holes are formed, and boron atoms are ion-implanted by ion implantation to form the base region 12, followed by CVD. A silicon oxide film is deposited to a thickness of 300 nm using a method, and the silicon oxide film is etched using an anisotropic etching method to leave silicon oxide films 13a and 13b on the side walls of the opening.
次に第１図に示すように多結晶シリコン膜１４を２５０
ｎｍ厚に堆積し、ヒ素原子をイオン注入法により添加し
た後熱処理を行いエミッタ領域１５を形成した後、写真
蝕刻法により多結晶シリコン膜１４を選択的に蝕刻した
後ベース引出し電極及びコレクタ引出電極取出し用開孔
を形成した後アルミニウム電ｔｆｉ１６ａ、１６ｂ、１
６ｃを選択的に形成する。Next, as shown in FIG.
After depositing the polycrystalline silicon film 14 to a thickness of 10 nm and adding arsenic atoms by ion implantation, heat treatment is performed to form an emitter region 15. After selectively etching the polycrystalline silicon film 14 by photolithography, a base extraction electrode and a collector extraction electrode are formed. After forming the extraction hole, the aluminum electrodes tfi16a, 16b, 1
6c is selectively formed.
なお、酸素イオン注入領域の代りに窒素イオン注入領域
（厳密にはイオン注入後熱処理をして窒化シリコンにし
たもの）を使用してもよい。Note that instead of the oxygen ion implantation region, a nitrogen ion implantation region (strictly speaking, a region made into silicon nitride by heat treatment after ion implantation) may be used.
この製造方法によると、酸素イオン注入領域と補償ベー
ス領域は自己整合的に形成でき、ベース領域中に酸素イ
オンが注入されて結晶性を劣化させたり抵抗値を増大さ
せることはない。According to this manufacturing method, the oxygen ion implantation region and the compensation base region can be formed in a self-aligned manner, and oxygen ions are not implanted into the base region to deteriorate the crystallinity or increase the resistance value.
以上説明したように本発明は、補償ベース領域直下に絶
縁膜を有しているのでベース抵抗低減化のなめに補償ベ
ース領域の濃度の増加を行った場合、あるいは、高速化
のためエピタキシャル成長層の薄膜化を行った場合も、
補償ベース領域と埋込コレクタ領域が近接することが無
く容量の増加、コレクタ・ベース耐圧の低下といった問
題を解決することが可能である。またセルファラインで
補償ベース領域直下にのみ絶縁膜を形成できるので、ベ
ース・エミッタ領域の結晶性の劣化、ベース領域の高抵
抗化といった間転は生じない。As explained above, since the present invention has an insulating film directly under the compensation base region, it is possible to increase the concentration of the compensation base region in order to reduce the base resistance, or to increase the speed of the epitaxial growth layer. Even when thinning the film,
Since the compensation base region and the buried collector region do not come close to each other, it is possible to solve problems such as an increase in capacitance and a decrease in collector-base breakdown voltage. Furthermore, since the insulating film can be formed only directly under the compensation base region in the self-alignment, problems such as deterioration of the crystallinity of the base/emitter region and increase in the resistance of the base region do not occur.
第１図は本発明の一実施例を示す半導体チップの縦断面
図、第２図＜ａ）〜（ｆ）は本発明の一実施例の製造方
法を説明するための工程順に配置した半導体チップの縦
断面図、第３図は従来の例を示す半導体チップの縦断面
図である。
１・・・シリコン基板、２・・・埋込コレクタ領域、３
ａ、３ｂ・・・エピタキシャル成長層、４ａ、４ｂ、４
ｃ、５．５ａ、５ｂ、７．７ａ、７１：ｌ。
１０．１：３ａ、 １３ｂ・−酸化シリコン膜、６゜６
ａ、６ｂ・・・窒化シリコン膜、８ａ、８ｂ・・・酸素
イオン注入領域、９ ａ 、 ９ ｂ 、 ９ ｃ 、
１４．−多結晶シリコン膜、１７ａ、１７ｂ・・・レ
ジスト膜、１Ｌａ、ｌｌｂ・・・補償ベース領域、１２
・・・ベース領域、１５・・・エミッタ領域、１６ａ、
１６ｂ１６ｃ・・・アルミニウム電極。FIG. 1 is a vertical cross-sectional view of a semiconductor chip showing an embodiment of the present invention, and FIGS. 2A to 2F are semiconductor chips arranged in the order of steps to explain the manufacturing method of an embodiment of the present invention. FIG. 3 is a vertical cross-sectional view of a semiconductor chip showing a conventional example. 1... Silicon substrate, 2... Embedded collector region, 3
a, 3b...Epitaxial growth layer, 4a, 4b, 4
c, 5.5a, 5b, 7.7a, 71:l. 10.1:3a, 13b - silicon oxide film, 6°6
a, 6b... silicon nitride film, 8a, 8b... oxygen ion implantation region, 9 a, 9 b, 9 c,
14. - Polycrystalline silicon film, 17a, 17b...resist film, 1La, llb...compensation base region, 12
...Base region, 15...Emitter region, 16a,
16b16c...aluminum electrode.
Claims (1)
レクタ領域、前記埋込コレクタ領域上に形成された第１
導電型のエピタキシャル成長層、前記エピタキシャル成
長層中に形成された第２導電型のベース領域、前記エピ
タキシャル成長層中に形成され前記ベース領域と連結し
た第２導電型の補償ベース領域及び前記ベース領域中に
形成された第１導電型のエミッタ領域よりなるバイポー
ラトランジスタにおいて、前記補償ベース領域と前記埋
込コレクタ領域の間に絶縁膜を有し、前記補償ベース領
域が前記ベース領域及び前記エピタキシャル領域を介し
て前記埋込コレクタ領域と接続されていることを特徴と
する半導体装置。a buried collector region of a first conductivity type formed on a silicon semiconductor substrate; a first conductive type buried collector region formed on the buried collector region;
an epitaxial growth layer of a conductivity type; a base region of a second conductivity type formed in the epitaxial growth layer; a compensating base region of a second conductivity type formed in the epitaxial growth layer and connected to the base region; and a compensating base region of a second conductivity type formed in the base region. In the bipolar transistor, the bipolar transistor includes an emitter region of a first conductivity type, and an insulating film is provided between the compensation base region and the buried collector region, and the compensation base region is connected to the buried collector region through the base region and the epitaxial region. A semiconductor device characterized by being connected to a buried collector region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087512A JPH02265247A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087512A JPH02265247A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02265247A true JPH02265247A (en) | 1990-10-30 |
Family
ID=13917040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1087512A Pending JPH02265247A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02265247A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241422A (en) * | 1991-01-16 | 1992-08-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH05243247A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Semiconductor device and manufacture thereof |
-
1989
- 1989-04-05 JP JP1087512A patent/JPH02265247A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04241422A (en) * | 1991-01-16 | 1992-08-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH05243247A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Semiconductor device and manufacture thereof |
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