JPH02265277A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02265277A JPH02265277A JP1087511A JP8751189A JPH02265277A JP H02265277 A JPH02265277 A JP H02265277A JP 1087511 A JP1087511 A JP 1087511A JP 8751189 A JP8751189 A JP 8751189A JP H02265277 A JPH02265277 A JP H02265277A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- region
- concentration impurity
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関”し、特にオフセットゲート型
のＭＯ８Ｉ−ランジスタの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an offset gate type MO8I transistor.
従来のオフセットゲート型の構造をもつ高耐圧。 High withstand voltage with conventional offset gate type structure.
ＭＯＳトランジスタ（以下オフセットＭＯＳと記す）で
は、ソース、ドレイン間に２００■以上の高耐圧を実現
するために、オフセット部の表面付近のみに、低濃度の
不純物を導入してドレイン領域を構成していた。以下第
２図を用いて説明する。In a MOS transistor (hereinafter referred to as offset MOS), in order to achieve a high breakdown voltage of 200μ or more between the source and drain, a low concentration of impurity is introduced only near the surface of the offset part to form the drain region. Ta. This will be explained below using FIG. 2.
第２図は、従来のＰ型オフセットＭＯ８の縦断面図であ
る６
Ｎ−型エピタキシャル層１上にはソース電極２、ゲート
電極３．ドレイン電極４が形成されており、ドレイン電
極４とゲート酸化膜８との間のフィールド酸化Ｊｌ（１
（Ｓｉ０２）５の下の表面付近には、オフセット部を構
成するためのＰ−型拡散領域６が形成され、Ｐ型拡散層
７ＡとＰ＋型コンタクト領域４Ａと共にドレイン領域を
構成している。FIG. 2 is a vertical cross-sectional view of a conventional P-type offset MO 8. On the N-type epitaxial layer 1, there is a source electrode 2, a gate electrode 3. A drain electrode 4 is formed, and field oxidation Jl(1) is formed between the drain electrode 4 and the gate oxide film 8.
A P- type diffusion region 6 for forming an offset portion is formed near the surface below the (Si02) 5, and forms a drain region together with the P-type diffusion layer 7A and the P+ type contact region 4A.
この構造において、Ｐ−型拡散領域６は非常に低濃度な
ため、完全に空乏化し、２００Ｖ以上の高耐圧が実現出
来る。In this structure, since the P- type diffusion region 6 has a very low concentration, it is completely depleted and a high breakdown voltage of 200V or more can be achieved.
上述した従来のオフセットＭＯ３は、２００Ｖ以上の高
耐圧を実現する場合も、５０Ｖ〜１５０Ｖ程度の比較的
低い耐圧を実現する場合も、同じ製造工程数を要すると
いう欠点がある。The above-described conventional offset MO3 has a drawback in that the same number of manufacturing steps are required whether a high breakdown voltage of 200V or more is achieved or a relatively low breakdown voltage of about 50V to 150V is achieved.
本発明の半導体装置は、ゲート酸化膜とドレイン電極と
の間に厚い絶縁膜が形成された半導体装置において、ド
レイン領域は前記ドレイン電極に接する高濃度不純物領
域と、該高濃度不純物領域に接し前記厚い絶縁膜下を前
記ゲート酸化膜の端部まで拡がる低濃度不純物領域とか
ら構成されているものである。In the semiconductor device of the present invention, in the semiconductor device in which a thick insulating film is formed between a gate oxide film and a drain electrode, the drain region has a high concentration impurity region in contact with the drain electrode and a high concentration impurity region in contact with the high concentration impurity region. A low concentration impurity region extends under a thick insulating film to the edge of the gate oxide film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
Ｎ−型エピタキシャルＮ１上には、ゲート酸化膜８を介
して形成されたゲート電極３と、Ｐ＋型ソース領域９に
接続するソース電極２と、Ｐ＋型コンタクト領域４Ａに
接続するドレイン電極４とが設けられており、ゲート酸
化膜８とドレイン電極４との間には厚いフィールド酸化
膜５が形成されている。A gate electrode 3 formed through a gate oxide film 8, a source electrode 2 connected to a P+ type source region 9, and a drain electrode 4 connected to a P+ type contact region 4A are formed on the N− type epitaxial layer N1. A thick field oxide film 5 is formed between the gate oxide film 8 and the drain electrode 4 .
そしてドレイン領域は、Ｐ′型コンタクト領域４Ａとゲ
ート酸化膜８とドレイン電極４間のフィールド酸化膜５
の下部をゲート酸化膜８の端部まで拡がるＰ型拡散領域
７とから構成されている。The drain region includes a P' type contact region 4A, a field oxide film 5 between the gate oxide film 8 and the drain electrode 4.
A P-type diffusion region 7 extends below the gate oxide film 8 to the end of the gate oxide film 8.
このように構成された本実施例によれば、５０〜１５０
Ｖ程度の耐圧を有すＭＯＳトランジスタを実現する場合
、第２図で示した従来例におけるＰ−型拡散領域を除く
ことができるので、それだけ工程を削減することができ
る。According to this embodiment configured in this way, 50 to 150
When realizing a MOS transistor having a withstand voltage of about V, the P- type diffusion region in the conventional example shown in FIG. 2 can be removed, so the number of steps can be reduced accordingly.
以上説明したように本発明は、ドレイン領域を、ドレイ
ン電極に接する高濃度不純物領域とこの高濃度不純物領
域に接し厚い絶縁膜下をゲート酸化膜の端部誹で拡がる
低濃度不純物領域とから構成することにより、比較的低
い耐圧の半導体装置を形成する場合の工程を削減できる
という効果がある。As explained above, in the present invention, the drain region is composed of a high concentration impurity region in contact with the drain electrode and a low concentration impurity region in contact with the high concentration impurity region and extending under a thick insulating film by dipping the edge of the gate oxide film. This has the effect of reducing the number of steps required to form a semiconductor device with a relatively low breakdown voltage.
第１図は本発明の一実施例の断面図、第２図は従来例の
断面図である。
１・・・Ｎ−型エピタキシャル層、２・・・ソース電極
、３・・・ゲート電極、４・・・ドレイン電極、４Ａ・
・・Ｐ＋型コンタクト領域、５・・・フィールド酸化膜
、６・・・ｐ−型拡散領域、７，７Ａ・・・Ｐ型拡散領
域、８・・・ゲート酸化膜、９・・・Ｐ＋型ソース領域
。
１ 圓FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... N-type epitaxial layer, 2... Source electrode, 3... Gate electrode, 4... Drain electrode, 4A.
... P+ type contact region, 5... Field oxide film, 6... P- type diffusion region, 7, 7A... P type diffusion region, 8... Gate oxide film, 9... P+ type source area. 1 circle
Claims (1)
された半導体装置において、ドレイン領域は前記ドレイ
ン電極に接する高濃度不純物領域と、該高濃度不純物領
域に接し前記厚い絶縁膜下を前記ゲート酸化膜の端部ま
で拡がる低濃度不純物領域とから構成されていることを
特徴とする半導体装置。In a semiconductor device in which a thick insulating film is formed between a gate oxide film and a drain electrode, the drain region includes a high concentration impurity region in contact with the drain electrode and a high concentration impurity region in contact with the high concentration impurity region under the thick insulating film. A semiconductor device comprising a low concentration impurity region extending to an end of an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087511A JPH02265277A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087511A JPH02265277A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02265277A true JPH02265277A (en) | 1990-10-30 |
Family
ID=13917011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1087511A Pending JPH02265277A (en) | 1989-04-05 | 1989-04-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02265277A (en) |
-
1989
- 1989-04-05 JP JP1087511A patent/JPH02265277A/en active Pending
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