JPH02265313A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPH02265313A
JPH02265313A JP1085950A JP8595089A JPH02265313A JP H02265313 A JPH02265313 A JP H02265313A JP 1085950 A JP1085950 A JP 1085950A JP 8595089 A JP8595089 A JP 8595089A JP H02265313 A JPH02265313 A JP H02265313A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
input signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1085950A
Other languages
Japanese (ja)
Inventor
Yoshio Akiyama
秋山 義雄
Atsushi Kinoshita
淳 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1085950A priority Critical patent/JPH02265313A/en
Publication of JPH02265313A publication Critical patent/JPH02265313A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To output directly a change in an input signal to minimize the time delay of a generated pulse by providing a function utilizing directly an input pin signal as a control signal not passing through a logic circuit to supply the control signal with faster response. CONSTITUTION:A signal from a delay circuit 3 and an input signal 1 are inputted to an exclusive OR circuit 7, from which the change in the input signal 1 is outputted directly as an output signal 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体回路にお1ける、入力信号に同期した
制御信号を供給する回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for supplying a control signal synchronized with an input signal in a semiconductor circuit.

〔従来の技術〕[Conventional technology]

第4図は従来のATD信号発生回路を示す回路図である
。図において(1)は入力信号、(2)は内部伝達信号
、(3)はATDのパルス幅制御用の遅延回路、(4)
はパルス発生回路、(5)は波形整形ドライバー(6)
は波形整形ドライバー(5)の出力信号を示す。第5図
は第4図の回路における各部の波形を示すタイミングチ
ャートである。
FIG. 4 is a circuit diagram showing a conventional ATD signal generation circuit. In the figure, (1) is an input signal, (2) is an internal transmission signal, (3) is a delay circuit for controlling the pulse width of ATD, and (4)
is the pulse generation circuit, (5) is the waveform shaping driver (6)
indicates the output signal of the waveform shaping driver (5). FIG. 5 is a timing chart showing waveforms of various parts in the circuit of FIG. 4.

次に動作について説明する。入力信号(1)をアドレス
バッファを介した後、遅延回路(3)及びパルス発生回
路(4)に入力させる。遅延回路(3)の出力を2つの
トランスミッションゲートに入力し、各1個がON又は
OFF動作を行う。このとき上記トランスミッションゲ
ートの入力にはそれぞれ反転信号が入力されており、第
5・図のA〜F各点の信号波形のように遅延回路(3)
で遅らせた時間分の幅だけl Lmの信号となるパルス
を発生することができる。
Next, the operation will be explained. After the input signal (1) passes through an address buffer, it is input to a delay circuit (3) and a pulse generation circuit (4). The output of the delay circuit (3) is input to two transmission gates, each of which performs an ON or OFF operation. At this time, an inverted signal is input to each input of the transmission gate, and the delay circuit (3)
It is possible to generate a pulse that becomes the lLm signal by the width of the time delayed by .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第5図に示すE点、F点の波形かられかるように受生パ
ルスの幅は第4図のA点の変化と遅延回路(3)の出力
の変化時間とで決められる。
As can be seen from the waveforms at points E and F shown in FIG. 5, the width of the received pulse is determined by the change in point A in FIG. 4 and the change time of the output of the delay circuit (3).

近年、高速化が進むにつれ、アクセス時間が速くなり、
その分、ATD信号の完了する時間も短くなってきてお
り、信号開始時間が遅れると、その分、パルス幅が狭く
なり、充分な動作ができなくなって来ている。例えば高
速S RAMで1ons品を作るにはATD信号として
は5nSでイコライズ解除と考える。するとパルス幅は
、入力からの遅延が2nSとして約3nSの幅で行う必
要が出てくる。
In recent years, as speeds have increased, access times have become faster.
Correspondingly, the time required for the ATD signal to complete is becoming shorter, and if the signal start time is delayed, the pulse width becomes narrower, making it impossible to operate satisfactorily. For example, to make a 1-ounce product with high-speed SRAM, the ATD signal is considered to be equalized at 5 nS. Then, the pulse width needs to be approximately 3 nS assuming a delay from the input of 2 nS.

パルス幅3nSでは内部の容量などを考慮しても充分と
は言えない。
A pulse width of 3 nS is not sufficient even considering internal capacitance.

この発明は1肥のような問題点を解消するためなされt
コもので、パルスの発生開始点を極力入力信号の変化に
近づけ、安定したパルスを供給することを目的とする。
This invention was made to solve problems such as 1 fertilizer.
The purpose of this is to bring the pulse generation start point as close to the change in the input signal as possible to supply stable pulses.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体回路は入力信号を直接使用し、出
力信号の開始点をより入力信号開始点に近づけることに
より、充分なパルス幅を確保するものである。
The semiconductor circuit according to the present invention uses the input signal directly and brings the start point of the output signal closer to the start point of the input signal, thereby ensuring a sufficient pulse width.

〔作用〕[Effect]

この発明に係る半導体回路は入力信号の変化とほぼ同時
にパルスを発生することができ、高速応答性に優れた作
用を有する。
The semiconductor circuit according to the present invention can generate a pulse almost simultaneously with a change in an input signal, and has an excellent effect of high-speed response.

〔実施例〕〔Example〕

以下、この発明の一実施例を図番こついて説明する0第
1図はATD信号発生回路を示す回路図である。図にお
いて、(1)〜(a) * (5) e (6)に付い
ては第4図の従来例に示したものと同等であるので説明
を省略する。(7)は排他的OR回路である。第2図は
第1図及び比較のために第4図の従来例におけるそれ、
ぞれの入力信号(1)と出力信号(6)の波形を示すタ
イミングチャート、第3図は第1図の回路に示す各部の
波形をシミュレーションによって得tこタイミングチャ
ートである。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an ATD signal generating circuit. In the figure, (1) to (a) * (5) e (6) are the same as those shown in the conventional example of FIG. 4, so their explanation will be omitted. (7) is an exclusive OR circuit. Figure 2 shows the conventional example shown in Figure 4 for comparison with Figure 1;
FIG. 3 is a timing chart showing the waveforms of each input signal (1) and output signal (6). FIG. 3 is a timing chart obtained by simulation of the waveforms of each part shown in the circuit of FIG.

次に動作について説明する。従来回路と同様の遅延回路
(3)による信号と入力信号(1)を排他的OR回路(
7)に入力することにより、入力信号(1)の変化を直
接出力信号(6)として出力することができる。
Next, the operation will be explained. An exclusive OR circuit (
7), a change in the input signal (1) can be directly output as an output signal (6).

第1図の回路各部の波形を示すと第2図及び第3図のタ
イミングチャートのとおりである。
The waveforms of each part of the circuit in FIG. 1 are shown in the timing charts of FIGS. 2 and 3.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば入力信号の変化を直接
出力でき、発生パルスの時間遅れを最小限に抑えること
ができる。
As described above, according to the present invention, changes in an input signal can be directly output, and the time delay of generated pulses can be minimized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すATD信号発生回路
の回路図、第2図は第1図及び第4図の回路におけるそ
れぞれの入力信号と出方信号の波形を示すタイミングチ
ャート、第3図は第1図の回路に示す各部の波形をシミ
ュレーションによって得たタイミングチャート、第4図
は従来のATD信号発生回路の回路図、第5図は第4図
に示す各点の波形を示すタイミングチャートである。 図において(1)は入力信号、(2)は内部伝達信号、
(3)ハ遅延回路、(5)は波形整形ド、ライバー、(
6) J、t 出力信号、(7月よ排他的OR回路を示
す。なお、図中、同一符号は同一、又は相当部分を示す
FIG. 1 is a circuit diagram of an ATD signal generation circuit showing an embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of input signals and output signals in the circuits of FIGS. 1 and 4, and FIG. Figure 3 is a timing chart obtained by simulation of the waveforms of each part shown in the circuit in Figure 1, Figure 4 is a circuit diagram of a conventional ATD signal generation circuit, and Figure 5 shows the waveforms at each point shown in Figure 4. This is a timing chart. In the figure, (1) is an input signal, (2) is an internal transmission signal,
(3) C delay circuit, (5) waveform shaping driver, (
6) J, t output signal, (July shows an exclusive OR circuit. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] ATD等回路制御用信号を有する回路において、制御信
号として入力ピン信号をロジックを介さず直接利用する
ことにより、より応答性の速い制御信号を供給する機能
を備えたことを特徴とする半導体回路。
A semiconductor circuit having a function of supplying a control signal with faster response by directly using an input pin signal as a control signal without going through logic in a circuit having a circuit control signal such as an ATD.
JP1085950A 1989-04-05 1989-04-05 Semiconductor circuit Pending JPH02265313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1085950A JPH02265313A (en) 1989-04-05 1989-04-05 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1085950A JPH02265313A (en) 1989-04-05 1989-04-05 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPH02265313A true JPH02265313A (en) 1990-10-30

Family

ID=13873040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1085950A Pending JPH02265313A (en) 1989-04-05 1989-04-05 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPH02265313A (en)

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