JPH02265322A - Output circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an output circuit for various logic ICs.

In recent years, various logic ICs, such as TTL type, 5TTL type logic, or 0MO3 type logic IC, are becoming faster and faster. Furthermore, there is a remarkable trend towards multi-pin ICs due to multi-functionality.

FIG. 4 is a diagram showing an example of an output circuit of a logic IC.
The output circuit 1 includes an H level output transistor T+Tlb and an L level output transistor T2 connected in a totem pole between an H level power line (hereinafter referred to as VCC) and an L level power line (hereinafter referred to as GND), and both of these. It includes an output terminal 2 drawn out from a connection point of the output transistors, and a phase split transistor T that makes one of the output transistors conductive in response to an input signal Vi. Note that T 4 and T s are transistors, RI to R
8 is a resistor, D+ is a Schottky barrier diode, 3
is an input terminal, ■. is the output signal.

In the output circuit 1 having such a configuration, when Vt is manually inputted at L level, Tlm and T1 are made conductive by T, and as a result, vo becomes H level, and on the other hand, when Vt is inputted at H level, When it is done, T.

As a result of making T2 conductive, vo becomes L level. Here, transistors such as T, a, T, , T, , T, etc. are equipped with Schottky barrier diodes, contributing to an improvement in operating speed.

Incidentally, in an IC including a plurality of output circuits 1 that operate at high speed, there is a known problem that when a plurality of outputs are changed simultaneously, the delay time of the output signal increases.

This is because the potential of the power supply and ground fluctuate due to the influence of outputs that change at the same time. For example, when the ground potential fluctuates to the negative side of OV, the potential rise of vo is delayed, and this causes the output signal to rise + H This is because the delay time at the time of change is extended.

FIG. 5 is a timing chart showing a specific example of such a problem. When the other output changes, the input signal Vi changes to VA.
When falling from N to ViL, it is desirable for the output signal V0 to rise immediately as shown by ■, but due to fluctuations in the ground potential due to changes in other outputs (fluctuations that fall to the negative side of OV). ■ The actual output signal in this case is affected. The rise of is any one of ■ to ■. Which of ■ to ■ is determined by the number of outputs that change simultaneously, and the larger the number, the longer the delay time becomes from ■→■→■.

[Conventional technology]

Conventionally, as a method to solve such delay time problems, a method has been adopted, for example, of slowing down the change in output (transient response).

[Problem to be solved by the invention]

However, the conventional method of slowing down the transient response has the problem of having to sacrifice high speed.

Therefore, an object of the present invention is to shorten delay time without sacrificing high speed.

[Means to solve the problem]

In order to achieve the above object, the output circuit according to the present invention has H
An H level output transistor and an L level transistor are connected in a totem pole between a level power supply line and an L level power supply line, an output terminal is drawn out from a connection point between these two output transistors, and both outputs are connected according to an input signal. In an output circuit including a phase sprint transistor that conducts one of the transistors, a diode and a resistor are connected in series to form a pull-up circuit, and the pull-up circuit is configured such that the cathode side of the diode faces the output terminal. It is characterized in that it is connected between the H level power supply line and the output terminal.

[Effect]

In the present invention, the potential of the output terminal is pulled up by the pull-up circuit.

Therefore, for example, potential fluctuations at the output terminal due to fluctuations in other outputs are suppressed, and the output signal changes quickly from L to H.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a diagram showing a first embodiment of an output circuit according to the present invention, and the same components as in FIG. 4 are given the same numbers.

In FIG. 1, 5 is a pull-up circuit, and the pull-up circuit 5 is . A resistor Ra and a Schottky barrier diode (diode) D are connected in series between , and V.
a, and a Schottky barrier diode Da
The cathode side (indicated in the figure) is connected with the output terminal 2 facing.

In such a configuration, when the input signal Vi changes from L to H, Tlm, T1 . changes from a conducting state (hereinafter referred to as on) to a non-conducting state (hereinafter referred to as off), while T2
changes from off to on, and the potential of the output signal v0 is set to L level.

Now, if the potential of the output terminal 2 attempts to change from 0■ to the negative side due to other outputs that change at the same time, the potential of the output terminal 2 changes from 0■ to the negative side through the pull-up circuit 5. , and the current 11 flowing from T2 to T2 suppresses the above fluctuation. As a result, the potential of the output terminal 2 is maintained near the L level. That is, when the input signal Vi changes to H-+L, the potential of the output terminal 2 rises from the potential maintained near the L level, resulting in an output signal (2). The delay time when changing from L to H can be shortened. Moreover, there is no need to delay transient response, so there is no need to sacrifice high speed.
By inserting Da into the pull-up circuit 5, it is possible to prevent current from flowing from the output terminal 2 to VCC even if the potential of the output terminal 2 becomes higher than VCC.

In this embodiment, since the pull-up circuit 5 consisting of Ra and Da is provided between VCC and the output terminal 2, it is possible to suppress potential fluctuations at the output terminal 2 caused by the influence of outputs that change simultaneously. The output signal v when the input signal Vt changes to H-4L level
The delay time when 0 changes from L to H can be shortened.

FIG. 2 is a graph simulating the delay time when the output signal v0 changes from L to H. In FIG. 2, the broken line is the input signal Vi, and the solid line is the output signal ■ when this embodiment is applied. , the virtual line is the output signal V, / when this embodiment is not applicable, and the delay time from the falling change of Vi to the rising change of vo is shown as Ta, while the delay time until vo' is shown as Tb. ing. That is, as a result of being able to effectively suppress potential fluctuations due to changes in other outputs, the delay time can be improved to Tb-+Ta.

Note that in the above embodiments, Ra is expressed as a resistance, but it is not limited to this. For example, as shown in FIG. 3, which shows a second embodiment of the output circuit according to the present invention, an N-channel M
O3) The transistor TN may be used as a negative resistance, and the pull-up circuit 6 may be configured by connecting a Schottky barrier diode (Da) similar to the first embodiment to this TH in series. However, a PN junction diode (diode) Db may be used instead of Da. This seems to be particularly effective in B i-CMO3 circuits.

〔Effect of the invention〕

According to the present invention, delay time can be shortened without sacrificing high speed.

[Brief explanation of drawings]

Fig. 1.2 is a diagram showing a first embodiment of the output circuit according to the present invention, Fig. 1 is a configuration diagram thereof, Fig. 2 is a graph showing the simulation result, and Fig. 3 is a diagram showing a first embodiment of the output circuit according to the present invention. 4.5 is a diagram showing a conventional output circuit; FIG. 4 is a diagram showing its configuration; and FIG. 5 is a graph for explaining the problem. be. ■. ,...H level power line, GND...L level! '61 L'A,T,
,,T,......H level output transistor, T
2...L level output transistor, T...
...Phase split transistor, Ra...
...Resistance, Da...Schottky barrier diode (diode), TN...N channel MO3) transistor (resistance) Db...PN junction diode (diode)
, 5.6...Pull-up circuit. Graph showing the simulation results of the first embodiment Figure 2 Block diagram of the first embodiment Figure 1 @ Figure Graph for explaining the conventional problems Figure 5

Claims (1)

[Scope of Claims] An H level output transistor and an L level output transistor connected in a totem pole between an H level power line and an L level power line, and an output terminal drawn out from a connection point between the two output transistors; In an output circuit equipped with a phase split transistor that conducts one of the output transistors according to an input signal, a pull-up circuit is configured by connecting a diode and a resistor in series, and the pull-up circuit is connected to a diode. An output circuit characterized in that the output circuit is connected between the H level power supply line and the output terminal with the cathode side facing the output terminal.