JPH022671A - Dynamic random access memory device - Google Patents

Abstract

PURPOSE:To prevent soft errors from being produced to raise operation reliability by forming a capacitor formed in a trench into a particular structure and further forming a conductive layer of a cell plate of said capacitor such that it extends through a central portion of the bottom of the trench to a semiconductor substrate for conduction. CONSTITUTION:The title device includes capacitors C1, C2 and a MIS transistor Q both formed in a trench 8 formed in a semiconductor substrate 1 of one conductivity type. The capacitors C1, C2 include a first dielectric layer 9 formed to cover therewith a periphery of the bottom of the trench 8 and the sides of the same, a first conductive layer 10 buried in the trench 8 covering the dielectric layer 9 and connected in an ohmic contact to any one region 6 of a source or a drain of a transistor Q, a second dielectric layer 11 formed to cover the conductive layer 10 therewith, and a second conductive layer 12 of an opposite conductivity type to that of the substrate 1 and buried in the trench 8 to cover the dielectric layer 11 therewith. Additionally, the conductive layer 12 is formed such that it extends through a central portion of the bottom of the trench 8 to be conductive with the substrate 1.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to prevent the occurrence of soft errors and increase operational reliability with respect to DRAM devices, particularly the structure of capacitor cells used in the devices. The capacitor includes a substrate, a capacitor formed inside a trench formed in the semiconductor substrate, and an MIS transistor formed in the semiconductor substrate for switching charging and discharging of charge to the capacitor. A first dielectric layer formed to cover the peripheral portion and sidewall portion of the bottom of the trench, and a source narrow page region of the M S transistor that is buried in the trench and covers the first dielectric layer. or a first conductive layer ohmically connected to either of the drain regions;
a second dielectric layer formed over the conductive layer;
a second conductive layer of a conductivity type opposite to that of the semiconductor substrate, the second conductive layer being embedded in the trench and covering the dielectric layer of the semiconductor substrate, the second conductive layer penetrating the center portion of the bottom of the trench; and is configured to be electrically conductive to the semiconductor substrate.

[Industrial Field of Application] The present invention relates to a Guinamink random access memory (hereinafter referred to as DRAM) device, and particularly to the structure of a capacitor cell used in the device.

DRAM cells are becoming smaller year by year due to demands for higher integration. As a result, the charge storage capacity has decreased, causing problems such as soft errors and a decrease in output voltage. For this reason, there is a need for a DRAM device that can realize a larger storage capacity with a smaller cell area while preventing malfunctions caused by soft errors and the like.

[Conventional technology]

FIG. 4 shows a cross-sectional structure of a memory cell in a DRAM device as an example of a conventional type.

The example in FIG. 4 is a buried and stacked capacitor cell (B
uried and 5tacked Capacit
BS CC1 46th Proceedings of the 46th Annual Conference on Applied Materials P, 423. October 1985).

In the figure, l is a p-type semiconductor substrate, 2 is a field insulating layer for defining a cell region, 3 is a gate insulating layer, 4 is a word line (gate electrode), and 5 and 6 are high concentration (n
"type" source and drain regions; 7 is a high concentration (p" type) region for blocking the operation of a parasitic transistor formed in the substrate; 8 is a trench formed in the substrate; 9a is a trench A dielectric layer of the capacitor formed on the side surface, 10a is a storage electrode of the capacitor, lla is a dielectric layer of the capacitor, 12a is a counter electrode (cell plate) of the capacitor, 13 is an interlayer insulating layer, and 14 is a source region 5. A bit line formed on the interlayer insulating layer 13 so as to be in contact with it is shown.

In the configuration shown in FIG. 4, a semiconductor substrate 1, a gate insulating layer 3, a word line (gate electrode) 4, a source region 5, and a drain region 6 form a memory cell using metal, oxide, and
Semiconductor (MOS) l-transistors, more broadly metal-insulator-semiconductor (MrS) transistors, are formed.

A first capacitor of the memory cell is formed by the semiconductor substrate 1 functioning as a counter electrode, the dielectric layer 9a, and the storage electrode 10a, while the storage electrode 10a, the dielectric layer 11a, and the counter electrode ( A second capacitor of the memory cell is formed by the cell plate 12a. In this way, by forming two capacitors using both the buried structure and the stacked structure, the capacitance of the capacitor is increased without increasing the area of each memory cell.

[Problem to be solved by the invention]

In the conventional structure described above, it is assumed that α rays enter the substrate as indicated by the arrows in the figure.

Such α rays (α particles) are often emitted from radioactive elements such as uranium and thorium contained in package materials and IC memory materials, but when the α particles enter the substrate, As shown in FIG. 4, electron-hole pairs (carriers) are generated.

In the illustrated example, the storage electrode 10a is covered with the dielectric layer 9a, so carriers (electrons in this case) generated within the substrate are not collected in the storage electrode 10a. Therefore, excess carriers, ie, electrons, generated in the substrate by the incidence of α particles are collected in the n4 type drain region 6 and source region 5, as shown by arrows in the figure.

In particular, since the drain region 6 is the part connected to the storage electrode 10a of the capacitor, if carriers are excessively collected in this region, the potential of the region decreases, and there is a possibility that stored information will be lost. arise. In other words,
A soft error occurs, causing the DRAM to malfunction.

The present invention was created in view of the problems in the prior art described above, and an object of the present invention is to provide a DRAM device that can prevent the occurrence of soft errors and improve operational reliability.

[Means to solve the problem]

The above-mentioned problems in the conventional technology can be solved by devising a cell structure so that excess carriers generated in the substrate due to the incidence of α particles or the like are not excessively collected in the source/drain regions of the transistor.

Therefore, according to the present invention, there is provided a semiconductor substrate of a conductive type, a capacitor formed inside a trench formed in the semiconductor substrate, and a switching method for charging and discharging charge of the capacitor formed in the semiconductor substrate. The capacitor includes a first dielectric layer formed covering the peripheral portion and sidewall portion of the bottom of the trench, and a transistor inside the trench covering the first dielectric layer. a first conductive layer embedded in the MISI disk and ohmically connected to either the source region or the drain region of the MISI disk; and a second dielectric layer formed over the first conductive layer. a second conductive layer of a conductivity type opposite to that of the semiconductor substrate, the second conductive layer is embedded in the trench and covers the second dielectric layer, and the second conductive layer is located at the bottom of the trench. There is provided a DRAM device characterized in that the DRAM device is formed so as to be electrically conductive to the semiconductor substrate through the central portion of the semiconductor substrate.

[Function] According to the above-described configuration, the excess carriers generated in the semiconductor substrate due to the incidence of α particles pass through the center portion of the bottom of the trench and connect to the second conductive layer formed to be electrically conductive to the substrate. Actively flows into the layers.

Therefore, the amount of carriers collected in the source or drain region of the transistor is relatively reduced, and fluctuations in the potential of the region are suppressed, so that the possibility of loss of stored information can be avoided. In other words, it is possible to prevent the occurrence of soft errors and improve the operational reliability of the DRAM.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the structure of a memory cell used in a DRAM device as an embodiment of the present invention.
(a) shows a cross section of the memory cell, and (b) shows its equivalent circuit.

In FIG. 1, 1 is a semiconductor substrate made of p-type silicon (Si), and 2 is silicon dioxide (Si) for defining a cell region.
3 is a gate insulating layer made of SiO□, 4 is a titanium silicide (TiSi
z), etc.; 5 and 6 indicate high concentration (n" type) source and drain regions, respectively; 7 is a high concentration (p' type) region; It shows a region that prevents a parasitic MOS transistor formed in the substrate from operating, that is, a region that functions as a channel stopper.

8 is a trench formed in the substrate including a field region, 9 is an insulating layer made of SiO□ formed on the side surface of the trench and serves as a dielectric of the capacitor, and IO is a region of the capacitor made of poly-Si. Storage electrode, 11
12 is an insulating layer made of SiO□ and functions as a dielectric of the capacitor; 12 is a counter electrode (cell plate) of the capacitor made of high concentration (n'' type) poly-Si;
13 is an interlayer insulating layer made of 5in2, 14 is in contact with the source region 5 through a contact hole, and the interlayer insulating layer 1
3 shows a bit line made of aluminum (AI) or the like extending in a direction perpendicular to the word line (gate electrode) 4. and,
Reference numeral 15 denotes an n-type region formed between the counter electrode (cell plate) 12 and the substrate 1;
It is formed by the diffusion of n-type impurities from poly-Si in the cell plate.

As shown in the equivalent circuit of FIG.
, a gate insulating layer 3, a word line (gate electrode) 4,
A MOS transistor (n-channel type) Q of the memory cell is formed by the source region 5 and the drain region 6,
Furthermore, a semiconductor substrate 1 functioning as a counter electrode (cell plate) and a dielectric material rF! J9 and the storage electrode 10 form the first capacitor C1 of the memory cell;
The storage electrode 10, the dielectric layer 11, and the counter electrode (cell plate) 127 form the second capacitor C2 of the memory cell.
is formed.

In this embodiment, a bias voltage of -3V is applied to the semiconductor substrate 1, and a bias voltage of 2.5V is applied to the counter electrode (cell plate) 12.
A voltage of ν is applied, and the potential of the storage electrode 10 is set to be 5V.

Next, a method for manufacturing the main part of the cell shown in FIG. 1, that is, the capacitor cell, will be explained with reference to the process diagrams in FIGS. 2(a) to 2(h).

First, in step (a), a 5iOz insulating layer for a pad is formed on a P-type Si substrate 1 by thermal oxidation, and then a P-type impurity, e.g. Boron (B) ions are implanted to form a channel stopper region 7. Next, the surface of the region 7 is oxidized to form a field insulating layer 2, and after removing the band SiO□ insulating layer, an SiO□ insulating layer (corresponding to the gate insulating layer 3) is formed, and then a 5iOz insulating layer is formed. After forming a gate electrode (not shown in FIG. 2) on the top, n-type impurity ions are implanted at a high concentration to form the source region (
2) and a drain region 6 are formed.

In the next step (b), a trench 8 is formed to a depth of about 4 μm in the Si substrate 1 in a predetermined region of the field insulating layer 2 using conventional lamination and reactive ion etching (RIE). .

In the next step (c), about 200 nanometers (20 nm
A SiO□ insulating layer 9 is formed with a thickness of m).

This corresponds to the dielectric of the first capacitor CI.

In the next step (d), chemical vapor deposition (CVD) is used to coat the entire surface of the substrate including the inner surface of the trench 8 with a
．． A poly-Si layer is formed with a thickness of 3 μm.

Next, using photolithography, other regions of the poly-Si layer are removed so that the region around the trench remains and the region ohmically connected to the drain region 6 of the transistor remains. do. This forms the storage electrode 10 of the capacitor.

In the next step (e), using the RIE method, the poly-Si layer 10 and the SiO□
Part of layer 9 is removed. As a result, the bottom of the trench once contacts the semiconductor substrate (p-type conductive region).

In the next step (f), in the same manner as in step (c), about 20% of
A Sin□ insulating layer 11 is formed with a thickness of 0.00 nm (20 nm). This corresponds to the dielectric of the second capacitor C2.

In the next step (g), in the same manner as in step (e), RI
SiO□ in the central part of the bottom of the trench by the E method
A portion of layer 11 is removed. This brings the bottom of the trench into contact with the semiconductor substrate (p-type conductive region).

In the last step (h), the dielectric WJ1 is formed using the CVD method.
An n゛゛ poly-Si layer doped with, for example, arsenic (As) or phosphorus (P) at a high concentration is grown on the surface of the capacitor 1 to the extent that the trench is sufficiently filled, thereby forming the counter electrode (cell plate) 12 of the capacitor. . Next, when heat is applied to about 1000° C., the n-type impurity contained in the poly-Si layer diffuses into the substrate, thereby forming an n-type region 15 near the bottom of the trench.

As a result, the counter electrode (cell plate) 12 and the substrate 1 are brought into conduction via the n-type region 5.

After that, according to the usual process, an interlayer insulating layer 13 is formed on the entire surface of the substrate, a contact window for wiring is opened on the source region 5,
A focus line 14 consisting of 8 liters is formed.

Next, the effects of the cell structure shown in FIG. 1 will be explained with reference to FIG. 3.

As mentioned above, in this embodiment, the storage electrode, that is, the polyS
Since the potential of the i-layer 10 is set high, a channel 16 and a depletion layer 17 are formed around the dielectric layer 9 of the capacitor, as shown in FIG.

In this state, as shown by the arrow in the figure, the α ray, that is, α
When particles enter the substrate, electron-hole pairs (carriers) are generated. Among the carriers generated by the incidence of α particles, some of the excess carriers (electrons in this case) naturally flow into the drain region 6 or source region 5 of the transistor, but most of them are caused by the electric field of the depletion layer 17. It flows into channel 16 (indicated by the arrow ■). These electrons flow within the channel and flow into the n-type region 15 at the bottom of the trench (indicated by the arrow ■). There is also a path that flows directly from the substrate to the n-type region 5 (indicated by the arrow ■).
.

In this way, the excess carriers generated in the semiconductor substrate 1 due to the incidence of α particles actively enter the n-type region 15, that is, the counter electrode (cell plate) 12 of the capacitor, through the paths ■, ■, and ■. Flow into. Therefore, the amount of carriers collected in the drain region 6 or source region 5 of the transistor is relatively reduced, and as a result, fluctuations in the potential of the region are suppressed. Therefore, it is possible to prevent the occurrence of soft errors, and even DR
The operational reliability of AM can be improved.

Although the above-mentioned embodiments have been described with respect to n-channel cells, it is clear that the present invention is not limited thereto and can be similarly applied to reverse p-channel cells.

〔Effect of the invention〕

As explained above, according to the present invention, the structure of the cell is devised so that excess carriers generated in the substrate due to the incidence of α particles etc. are not excessively collected in the source/drain regions of the transistor, thereby reducing soft errors. This can be prevented, thereby increasing operational reliability.

[Brief explanation of the drawing]

1(a) and (b) are diagrams showing the structure of a memory cell used in a DRAM device as an embodiment of the present invention, in which (a) is a cross-sectional view, (b) is an equivalent circuit diagram, Figures 2 (a) to (h) are manufacturing process diagrams of the main parts of the cell shown in Figure 1, Figure 3 is a sectional view to explain the effects of the cell structure shown in Figure 1, and Figure 4 is the conventional type. FIG. 2 is a cross-sectional view showing the structure of a memory cell in a DRAM device as an example. (Explanation of symbols) ■... Semiconductor base + JiCp type), 2... Field insulating layer, 3... Gate insulating layer, 4... Word line (gate electrode), 5... Source region (n "Type), 6...
Drain region (n' type), 7... Channel stopper region (p" type), 8... Trench, 9... Insulating layer (dielectric layer of capacitor), 10... Storage electrode of capacitor, 11... Insulating layer (dielectric layer of capacitor), 12
...Capacitor counter electrode (cell plate), 13.
...Interlayer insulating layer, 14...Bit line, 15...N-type region Q...Transistor, CI, C2...Capacitor. Manufacturing process diagram of the main parts of the cell shown in Figure 1. Figure 2 1... Semiconductor substrate (p type) 2°° Field insulating layer 3... f-) Insulating layer 4... Word line ( (gate electrode) 5... Source region (n+ type) Trench insulating layer (ca/shita dielectric layer) Capacitor/ε-shita storage electrode insulating layer (capacitor/dielectric dielectric layer) Cross-sectional view (b) Equivalent circuit diagram of the opposite electrode (cell pre-interlayer insulating layer bit line...n+ type region a)
16...Channel 17...Depletion layer of a memory cell in a DRAM device as an example of a conventional type. Cross-sectional diagram showing the structure

Claims (1)

[Claims] A semiconductor substrate (1) of one conductivity type; a capacitor (C1, C2) formed inside a trench (8) formed in the semiconductor substrate; The capacitor includes a MIS transistor (Q) that performs charging/discharging switching of a capacitor, and the capacitor includes a first dielectric layer (9) formed to cover the peripheral portion and sidewall portion of the bottom of the trench. and the M layer is buried in the trench and covers the first dielectric layer.
A first ohmically connected region (6) of either the source region or the drain region of the IS transistor.
a second dielectric layer (11) formed to cover the first conductive layer; and a second dielectric layer (11) formed to cover the second dielectric layer and embedded in the trench. It has a second conductive layer (12) of a conductivity type opposite to that of the semiconductor substrate, and the second conductive layer is formed so as to be electrically conductive to the semiconductor substrate through a central portion of the bottom of the trench. A dynamic random access memory device characterized by: