JPH0226748B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an IC test method that can easily test the logic functions of an IC.

Technical Background of the Invention and Problems Thereto Conventionally, IC tests have included tests of DC characteristics, AC characteristics, and logical value functions, and were performed using an IC tester. Among these IC tests,
Logic function testing involves applying a test pattern from the input terminal, operating the circuit inside the IC, and checking the resulting output pattern from the output terminal to see if it matches the correct output pattern expected in advance. It was tested depending on whether it was or not.
According to this method, when the logic function of the IC to be tested is only a combinational circuit, the test can be easily performed because any pattern can be selected as the test pattern to be input to the input terminal. However, in the case of a sequential circuit, the output pattern of the test result depends not only on the pattern input to the input terminal, but also on the output pattern of the flip-flop inside the IC, and it is not possible to directly input any pattern to this flip-flop from the input terminal. Testing was not easy because of the difficulty of Therefore, as a conventional method to improve this, all the flip-flops inside the IC are connected in series to form a shift register, and a clock to operate as a shift register, an input terminal for shifting in, and an input terminal for shifting out. An IC that tests the IC by adding an output pin and a pin to determine whether to use it as a shift register, in other words, whether to test it or not, so that any pattern can be set directly from the outside to the internal flip-flop.
A test method was also conducted. However, this shift register method also had the drawback of requiring a large amount of testing time, as the test pattern was sent from the outside to all flip-flops in series, 1 bit at a time, and set.

Furthermore, it has the disadvantage that 3 to 4 terminals must be added exclusively for testing.

Furthermore, when testing using an IC tester,
Connect all input/output terminals of the IC and the IC tester with wires, and the IC tester inputs the test pattern to the IC.
Since the IC tester reads and inspects the IC's output pattern, only one IC could be tested at the same time. In addition, as IC integration increases, the number of input/output pins increases, and the number of test patterns and output patterns also increases, so IC testers are required to have higher performance, making IC testers more expensive. A problem arose.

OBJECT OF THE INVENTION An object of the present invention is to provide an IC test method that can quickly and easily test the logical functions of a sequential circuit IC.

Another object of the present invention is to provide an IC test method that requires less increase in the number of test-dedicated terminals.

Another object of the present invention is to provide an IC test method that allows testing using a simple IC tester.

Summary of the Invention The present invention includes a first read-only memory in which a test pattern is written inside an IC, a second read-only memory in which a correct output pattern of the test result is written, and a matching circuit that determines whether the test result is correct. This is an IC test method in which the test pattern is used to test the IC, and the output of the matching circuit is checked to see if there is a failure in the logic function of the IC.

Embodiments of the Invention Examples of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is the entire IC according to the present invention. 2 is a combinational circuit that determines the logic of the IC's operation. 3 is a flip-flop which is operated by the clock input from the clock terminal 13. 4
is the first read-only memory (ROM; Reacl Only Memory) in which a test pattern for testing the logic function of IC1 is written in advance at the manufacturing stage.
and 40 is its output port. There are two ports: an output port 40, an external pattern output 41, and a flip-flop pattern output 42.

Reference numeral 5 denotes a second read-only memory (ROM) in which the correct test result output pattern is written in advance at the manufacturing stage, and the outputs are a correct external pattern output 51 and a correct flip-flop pattern output 5.
There are 2 ports. 6 is an address counter that supplies addresses to the first ROM 5 and the second ROM 6, and counts up by 1 by the clock input from the clock terminal 13. 9 is an input terminal from the outside of the IC, and 10 is an output to the outside. It is a terminal.
Reference numeral 11 is a test control circuit that outputs a corresponding control signal when testing the IC. 12 is a test terminal, and IC1 starts a test when a pulse is inputted to this terminal from the outside. 13 is a clock terminal, which is a terminal for inputting a clock. Reference numeral 14 is a match terminal, which outputs the test result. 20 is an input section to the combinational circuit 2, which includes an external input 21 and a flip-flop input 2.
2 ports. Normally (when no test is being performed), the external input 21 is input from the input terminal 9, and the flip-flop input 22 is input from the flip-flop 3. On the other hand, during testing, the external input 21 is the external pattern output 4 of the first ROM 4.
1 and the flip-flop input 22 is the first
Flip-flop pattern output 42 of ROM4
Enter from. This switching is done by multiplexer 8.
Do it with Of these, 81 switches between the input terminal 9 and the external pattern output 41, and 82 switches between the output of the flip-flop 3 and the flip-flop pattern output 42. Reference numeral 25 denotes an output section of the combinational circuit 2, which is composed of an external output 23 that is output to the output terminal 10 and a flip-flop output 24 that is sent to the flip-flop 3. The external output 23 is further connected to one input of the first matching circuit 71. On the other hand, the flip-flop output 24 is connected to the input of the flip-flop 3. 71 is a first matching circuit that checks whether the output pattern of the external output 23 and the output pattern of the correct external pattern output 51 match. 7
Reference numeral 2 designates a second matching circuit for checking whether the output pattern of the flip-flop 3 and the output pattern of the correct flip-flop pattern output 52 match. Reference numeral 73 is an AND circuit that outputs an output only when the first matching circuit 71 and the second matching circuit 72 both match. The output of AND73 is connected to match terminal 14.

Next, the test method will be explained.

The IC under test shall be tested by an IC tester.

The IC tester sends a pulse to test terminal 12 to start the test. The test control circuit 11 prepares to test the IC accordingly. That is, the address counter 6 is set to the test start address 1, for example, 0 address 1, the flip-flop 3 is cleared, and the selection of the multiplexer 8 is set to the first address.
Make it the output side of ROM4. As a result, the external input 21 and the flip-flop input 22, which are the inputs of the combinational circuit 2, are connected to the output 4 of the first ROM 4 instead of the input terminal 9 and the output of the flip-flop 3.
Turn to the 0 side.

This will start the test. First, the first test pattern is read out from the first ROM 4 and passed through the multiplexer 8 to the combinational circuit 2.
Enter. Among the test results based on the input test patterns, the output pattern from the external output 23 is sent to the first matching circuit 71 and then stored in the second ROM.
It is checked whether the output pattern matches the output pattern of the correct external pattern output 51 of No. 5. If it matches,
If so, the output of the first matching circuit 71 becomes 1. On the other hand, the flip-flop 3 cleared by the test start pulse and the output pattern (0 in this case) of the correct flip-flop pattern output 52 of the second ROM 5 are sent to the second matching circuit 72, and are matched. You can check whether it is there or not. If they match, the output of the second matching circuit 72 becomes 1 and
The output of 73 is 1. As a result, matching terminal 14
becomes 1 and is sent to the IC tester. The IC tester side monitors the value of the match terminal 14, and if it remains 0, it determines that there is a failure, stops the test, and moves on to testing the next IC. If it becomes 1, the IC tester determines that there is no failure up to that point, sends one clock to the clock terminal 13, and proceeds to the next step. When the IC under test 1 receives a clock, it sets a value in the flip-flop 3 according to the output pattern of the flip-flop output 24 generated by the first test pattern of the previous test, and also counts up the value of the address counter 6 by one. do. As a result of the count up, the output 40 of the first ROM 4 will output the second test pattern, and the output 50 of the second ROM 5 will output the correct test result pattern. The test for the presence or absence of a failure is carried out in the same way as before. That is, the output pattern of the external output 23 is inspected by the first matching circuit 71.
A second matching circuit 72 examines the output pattern of the flip-flop 3. By testing the output pattern of the flip-flop 3, not only the operating function of the flip-flop 3 itself is tested, but also the output pattern of the flip-flop output 24 based on the previous first test pattern is tested at the same time. This is because if the output pattern of flip-flop output 24 is wrong,
This is because flip-flop 3 should be set to an incorrect value. In other words, the second coincidence circuit 7
The test performed in step 2 is not only to test the operating function of flip-flop 3, but also to test the flip-flop output 2.
The output pattern appearing on the 4th side is also inspected.

At this point, the output results of the external output 23 according to the first and second test patterns, the output results of the flip-flop output 24 according to the first test pattern, and a part of the operational functions of the flip-flop 3 have been completed.

Repeat the above steps. Even after the last test pattern is completed, if there is no abnormality when the output state of the match terminal 14 is monitored by the IC tester, the IC is determined to be a good product.

Effects of the Invention As described above, according to the present invention, an IC tester inputs a pulse to the test terminal 12 to prompt the IC under test to start a test, and then
Clock to clock terminal 13, match terminal 14
Testing is easy because all you have to do is monitor the output. Furthermore, since the number of connections to terminals is small and the control of the terminals is simple, it is possible to test a plurality of terminals at the same time. Since you can test one test pattern with one clock, you can test at high speed. Additionally, since it is easy to control signals to the IC under test, testing can be done with a simple circuit without using an IC tester. Therefore, even after it has been incorporated into a system, a test circuit can be added and tested when the IC under test goes into standby mode or when it is started up. This has the characteristic of increasing the reliability of the system. Another advantage is that the addition of test input/output terminals only requires 2 piu of the test terminal 12 and the match terminal 14.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an IC to be tested according to the present invention. 1... Entire IC under test, 2... Combinational circuit,
3...Flip-flop, 4...First ROM,
5...Second ROM.

Claims (1)

[Scope of Claims] 1. Consists of a combinational circuit, a flip-flop operated by an external clock, an input terminal from the outside, and an output terminal to the outside, and a test pattern is input to the input terminal and the flip-flop, and the test pattern is inputted to the input terminal and the flip-flop. a first output pattern to the external terminal in response to the pattern; and a second output pattern from the flip-flop after inputting the clock and loading it into the flip-flop.
In the IC testing method, the logical function is tested by inspecting the output pattern of the IC, the IC having a first read-only memory in which the test pattern is written in advance in the IC; a second read-only memory (ROM) in which the correct answers of the first and second output patterns appearing at the output of the flip-flop and the flip-flop are written in advance; It has a match circuit that checks for a match, and a match terminal that outputs the output of the match circuit to the outside of the IC, and when testing the logic function of the IC, the test pattern written in the first ROM is used. , An IC test method characterized in that a test is performed by inspecting the test result appearing on the matching terminal.