JPH02267603A - Sequence controller - Google Patents

Abstract

PURPOSE:To attain a complicated processing action for control with use of a sequence table by using an input condition collecting instruction order group, a branch condition collecting instruction group, an output instruction group, etc., so as to put the logical and arithmetic expressions into the sequence table. CONSTITUTION:A sequence table contains an input condition collecting instruction group 30, a branch condition collecting instruction group 31, and a table instruction/output instruction group 32. A coupling means is added to secure the organic coupling among those instruction groups in accordance with the sequence working conditions. In this case, the coupling means consists of a bit accumulator for bit arithmetic, a word accumulator, a table No accumulator which holds the table No under execution, a pointer accumulator, an input data area, and a branch condition area. In such a constitution, the logical operation expression and arithmetic operation expression can be carried out via the sequence table.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequence controller that performs programmable sequence control operations.

[Conventional technology]

Conventional sequence tables and sequence control methods included in this type of sequence controller are shown in FIGS. 4 to 7. Furthermore, FIGS. 8 to 11 are explanatory diagrams of control operations of a general sequence controller,
In the system configuration diagram including the sequence controller shown in FIG. 8, 1 is a sequence controller, 2 is a tank for mixing liquids A and B, 3 is a mixer for liquids A and B,
4 is pulp for liquid A, 5 is pulp for liquid B, 6 is pulp for mixed liquid discharge, T is a motor for rotating the mixer 3, 8 is a start push button switch, 9 is for canceling a failure stop Push button switches 10, 20, and 30 are level switches for determining to what position in the tank 2 the liquid has been poured. 9. Pulp 4 is controlled by output 04 of sequence controller 1 and opened by logic 111, 10
” to close.

Similarly, pulp 5 is controlled with output 05, and pulp 6 is controlled with output 06. The motor 7 is controlled by the output 07, and the operation is started with the logic 111 and stopped with the logic '01. The start pushbutton switch 8 is an input I8. The push button switch 9 for canceling the failure stop is connected to the input crab 9, and the logic ``11'' turns ON, and ``O'' turns OFF.
Becomes FF. Level switch 10.20.30 is input 1
10, I20, and I30 are connected to the respective level switches 1G and 20.If the liquid level exceeds 30, logic 111 is disabled, and if it is below, logic 111 is disabled.15 is a warning lamp and outputs 0.
Connected to 15, logic 111 turns ON, and logic "O" turns OFF.

Further, FIG. 4 is a sequence table describing the operating procedure for controlling the system shown in FIG. 8. The detailed structure of the sequence table in Figure 4 is that it consists of the variable data table in Figure 10, the detailed data table in Figure 9, and the fixed data table in Figure 6, and its execution is performed using the table shown in Figure 5. It is executed by periodically executing execution instructions. Since the sequence controller 1 can execute a number of such tables, the table to be discussed here will be table 1.

FIG. 7 is a schematic flowchart of the table execution command.

Next, the operation shown in FIG. 8 will be explained below with reference to the sequence table shown in FIG. 4. First, in the sequence table, step STI waits for the start push button switch 8 to be turned ON (the switch 8 becomes logic "11").When it is turned ON next, the normal Mll becomes logic 11@, and the process goes to step ST2. Transition.

At that time, the output process 04 of step ST2 is executed (only the liquid A valve 4 has logic 111, all other outputs have logic 101), and liquid A is injected into the tank 2. When the level reaches the middle level due to liquid injection (both inputs I20 and I30 become logic 111), normal Ml
If l is logic 119, the process moves to step ST4. (Steps ST3 and 5.8 are abnormal processing) At that time, step ST
Output process 05 of 4 is carried out (only pulp 5 for liquid B is logic 11 open, other outputs are logic 101), and liquid B is injected into tank 2. Next, when the liquid level is high, (all inputs, IIO, I20, and I30 are logic 111), the process moves to step ST6.Hereafter, motor 7
Activate output 07 of the tank 2 to perform mixing processing, open output 06 of the mixed liquid discharge valve 6 to discharge the liquid inside the tank 2 until the tank 2 is empty, and set the entire output to logic 10 in step ST9.
After setting it to 1, the process returns to step STI again. The above is a case of normal sequence operation.

In addition, the table execution command "EXE TBL" in Figure 5
1'' periodically, the sequence table operates, and its execution flowchart is shown in FIG. 7 (the operation in FIG. 7 will be described later).

Also, Figure 6 shows the fixed data table, and the fourth
The address part in the sequence table shown in the figure is stored.

Furthermore, FIG. 9 shows a detailed data table for each step, and the data section in the nine sequence table shown in FIG. 4 is specifically stored in the following code.

For example, for the data for step STB, the output data is IOH, the output mask data is OFH...the first 4 data are blank, so the input data is IOH, the input mask data is OFH...the first 4 data are blank, so it is a rounded branch. Destination 1 is 02H (2 is written) Divergence 2 is 00H (blank) Divergence 3 is OOH (blank) Monitoring timer value is 10H (temporarily set to IOH) Step timer value is 10H (temporarily set to IOH) ) Also, the output data for step STZ is 0IH (only the first output is 1w, so it is OIH), and the output mask data is OOH (sixth OOH with no blank space)
) The input data is the input mask data, the branch destination 1 is the branch destination 2, the branch Nn3 is the monitoring timer value, the step timer value is 6H 8H 4H 0H 3H 64H (100 seconds) 0H Also, Figure 10 shows the variable data table. Store variable information in the table as shown. For example, the step destination indicates the current step destination, and for example, the sequence operation is step S.
If it is in TI, it becomes OIH.

The status flag stores the status of the table, and its details are shown in FIG. That is, the RUN flag is a flag that controls the execution/stopping of the table, and in this example, it is assumed that the logic Jl is in the "it" or "running" state.

The input condition fulfillment flag is logic 11" when the input value matches the value listed in the address table, and logic I when they do not match.
It becomes OI. For example, if the sequence operation is at step ST3 in FIG. 4, l30=1, I20=0
, 111 when 110=0, and 101 otherwise.

Input I8. Since I9 is blank, it is not included in the check conditions.

The step timer ffUP is reset by the output process executed at the beginning of the step, and is activated at the step timer value of that step shown in FIG. Time U
When P, the logic becomes 1111.

The monitoring timer UP operates in the same way as the step timer.

The step transition flag is used to determine whether output processing should be performed.

Next, the flowchart shown in FIG. 7 will be explained. That is, when the table execution instruction "EXE TBLI" starts, it is checked whether @11 is set in the RUN bit in the status flag shown in FIG. 11 (step 5TIO). If 111 is set here, the process moves to the next step and the step transition flag Jl is checked (step 5TII). At that time, if YES, output processing is executed (step 5T12).

What is output processing? Output specified data to the address of the output address table in the fixed data table of FIG.
, outputs 071C"O". In a blank space such as step ST3, a no-operation flag is passed, and the input condition fulfillment bit, step timer UP bit, and monitoring timer UP bit of the status flag shown in FIG. 11 are reset, and the step timer and monitoring timer are activated.

Next, the step transition 72 in FIG. 11 is reset to end the output process (step 5T13). If the step transition 7 lag "11" is not set in step 5TII, the input condition check process shown in FIG. 11 is performed (step 5T14).Here, the input condition check process refers to IIO, I20, I30.

I8. The data in I9 is sequentially read and if all match with the designated values, the input condition fulfillment bit of the status flag is set to logic 111, and if they do not match, it is set to 101. For example, in step ST2, 110="0" and I20="l".

Set to 111 when l30="l", otherwise set to 10''
Make it. (Since I8 and I9 are blank, these two conditions are considered to be satisfied.) Subsequently, timer processing is executed (step 5).
T15).

Timer processing is processing that updates the UP waiting time of the step timer and monitoring timer activated in the output processing, and sets the UP bit of the step timer and monitoring timer when a predetermined UP time is reached. The time limit value is designated for each step as shown in FIG. Next, it is checked whether the branch condition is met (step 5T16).

For example, in step ST2, the branch condition is met, which means that M11 is normal.
(Referring to the pit where the condition is met) becomes logic 111. Or abnormality M17 (monitoring timer UP bit)
When becomes 111, the condition is met. If the conditions are met at the same time, priority is given to the one written above, and priority is given to the normal Mll. Timer M120 is blank, so M12 is 1.
Even if it becomes 11, the branch condition is not satisfied.

If the result of checking whether the branch condition is met is YES, step update processing is performed (step ST17).

Here, the step update process is a process of rewriting the step address in FIG. 10 to a new step.

For example, in step ST2, the step destination is Sr1, but if the normal Ml1 branch condition is satisfied, the process moves to step ST4K. The step position is rewritten to Sr4. Subsequently, a step transition flag is set (step 5T18) and all processing operations are completed.

Next, the abnormal state will be explained. If a valve, a level switch, etc. are out of order and an abnormal state in which the input conditions are not satisfied continues, the monitoring timer UP for the abnormality M17 is established as in step ST2 before the normal Mll is established, and the process jumps to step ST3. In step ST3, output 015 is 1
1 @ and the alarm lamp turns on. Correspondingly, the operator checks the status of the plant, and if it is possible to take some action, press the button 9 to cancel the failure stop.
Press.

Then, the normal Mll becomes 111, step ST2 is executed again, the alarm lamp is turned off, and if there is no problem, the normal state is restored.

The same abnormal operation is performed in step ST5.8 below.

[Problem to be solved by the invention]

Since the conventional sequence controller is configured as described above, there is a problem in that it is not possible to directly input logical expressions and arithmetic expressions into the address section of the sequence table.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a sequence controller that can directly enter logical expressions and arithmetic expressions in the address section of a sequence table.

[Means to solve the problem]

The sequence controller according to the present invention has a sequence table including a group of input condition collection instructions, a group of branch condition collection instructions, a table instruction, and a group of output instructions, and has a coupling means for organically coupling each of them in accordance with the sequence operation conditions. It is prepared.

[Effect]

Since the sequence table in this invention can set an input condition collection instruction group, a branch condition collection instruction group, a table instruction, and an output instruction group, logical operation expressions and arithmetic operation expressions can also be executed on the sequence table.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an example of a sequence table according to the present invention, which is composed of an instruction table in FIG. 2, a detailed data table in FIG. 9, and a variable data table in FIG. 10.

First, the sequence controller 1 shown in FIG. 8 includes a bit akimulator (BAC') for bit operations, a word akimulator (WAC), a table akimulator (TAC) that holds the address of the table being executed, and a pointer. It is assumed that there is an Akinimulator (PAC), an input data area, and two branch condition areas. These are one implementation of the coupling means.

Next, the operation of the instruction table shown in FIG. 2 will be explained.

(1) <Operation of BEG TABLE 1 instruction> The table block to be executed from now on is the logic 11m in the BEGTBLI instruction, so the logic 111 is written to the table block accumulator TAC. Also,
The RUN bit of the status flag in the table 111 is read and its value is written to the bit akine mulrator BAC.

(2) <Operation of BN + 38 instructions> If the value of the bit accumulator BAC is @11, the process goes directly to the next instruction, but if it is '01, it branches to the 38 instructions ahead, the tυEND TBL instruction.

When combined with the BEG TBL "1" instruction, a branch occurs when the RUN bit is 101, Rima] Table 11
1 will not be executed. Here, for ease of discussion, the RUN bit is 111, and the table is 11.
shall be carried out.

<Operation of 3K SA IN instruction> Set the start address of the input data area to the pointer accumulator PAC.

(Step 4: Operation of IIO command) 110 (ON/OF of level switch 10 in Fig. 8)
F information) and writes it to the pit accumulator BAC.

(5) <Operation of ORI 11 instruction> Ill (Il
(l will be explained later), performs a logical OR operation with the value of the pit accumulator BAC, and writes the result to the bit accumulator BAC.

(61 <BIT TF instruction>) Transfers the value of the bit accumulator BAC using the contents of the pointer accumulator PAC as address information.

After that, the contents of the pointer akimulator PAC are incremented by 1.

The process is the same as above until the command 30~;19BITTF.

From 5AIN instruction; up to I9 BIT TF instruction,
Input check condition data, thumbnails, etc. in the input data area.
? The OR value of 110 and Ill to the value of step 9 will be sequentially transferred.

(7) <SA JMP~; M13 BIT TF
Operation at t> The SA JMP instruction is an instruction that sets the starting address of the branch condition area in the pointer accumulator PAC. The branch condition M is similar to the input check data below.
The values of 11, M12, and M17 are sequentially transferred to the branch condition area.

(8) <Operation of DOTBL instruction> A schematic flow of the DOTBL command is shown in FIG.

In the input condition check process of step 5T20, if the input data (values in the input data area) and the predetermined values all match, the input condition fulfillment bit of the status flag is set to logic 111.
The difference from the conventional method is that data reading is performed in the preprocessing of the input condition collection command group 30.

Next, in the timer processing of step 5T21, the UP waiting time of the step timer and the monitoring timer activated in the output processing is updated, and when the predetermined UP waiting time is reached, the step timer IF and the UP bit of the monitoring timer are set. The time limit value is the 9th
It is specified for each step shown in the detailed data table in the figure. Same as before.

In step 5T22, when the branch condition is met, the contents of the six branch condition areas that have been inserted in advance are checked to see if the branch condition is met.

In step update processing at step 5T23, the step address in FIG. 10 is rewritten to a new step. Same as before.

Next, in the output processing in step 5T24, the input condition satisfied bit of the status flag, the step timer UP bit, and the monitoring timer UP bit are reset, and the step timer and monitoring timer are started with the time limit values described in the step, and the actual output is executed. pointer aki.

- Configure the mulator PAC. For example, if it is just before the execution of step 2, step 2 of the fixed data table in Figure 9
Pointer to the beginning of the output data of PAC
starts to point.

(9) <Operation of BN+15> If the branch condition is not met with the Do TBL instruction, the value of the bit akine mulrator BAC is 101, so END TBL
This means that the branch and output instructions will be executed until the end.

αI <SJMP *+2 operation> Check the output mask data pointed to by the pointer akine mulrator PAC, and if the logic is 111, jump to the next instruction (at this time, the next output instruction will not be executed), and if it is “01”, output Read data bit akinimulator BA
Set it to C and execute the next command. In the final processing of this instruction, the value of the pointer akimulator PAC is counted UPL, and is made to point to the next output mask data and output data.

Ql) <→04 operation> Outputs the value of the bit akine mulrator BAC to 04.

For example, with the combination of SJMP rice +2 and →04, step l
In this case, 01 is output to 04, 1 is output to 04 in step 2, and no processing is performed in step 3.

The following combination of SJMP and → command is similar, but an explanation will be added regarding the last output command.

;KO...10'' is written to the word akinemulator WAC.

#Kl...When the value of bit accumulator BAC is 1, Jl is written to word accumulator WAC, but pit accumulator BAC is 0.
When it is 1, there is no operation.

+ EWO...Adds the value of EWO to the value of the word akine muller WAC.

→EWO...Writes the contents of word accumulator WAC to EWO.

Therefore, the processing of the fifth output command is as follows.

In step 2, 015 is @01, EWOIc is 1
Since 0@ is added, the value does not change. In step 3, 015 becomes 111, and 111 is added to EWO. In other words, EWO can store the number of occurrences of abnormal processing.

a3<ENDTBL (D operation> It indicates the end of the instruction table and does not perform any operation.

Next, the operation of the present invention will be explained below with reference to the sequence table shown in FIG. First, the control operation is step 1.
Suppose it is in When the start push button switch 8 is pressed, the input crab 8 becomes 111, the normal Mll branch condition is satisfied with the Do TBL command, and the step update process and output process of DOTBL are executed. BN right after DOTBL US + 1
5, the bit akine mulrator BAC is 111, so the branch is not taken, and the output instruction group 32 is executed (in this case, step S
output of T2). Then, an input condition collection instruction group 301 and a branch condition collection instruction group 31. This is the process of executing Do TBL in FIG. 3 and finding the branch condition.

Here, Ill, I21, and I31 are each set to 110. to increase the reliability of the level switch. I20. I30
This is the input of a level switch installed at the same level as .

EWO stores the number of occurrences of abnormal processing.

In a simple plant example as shown in Figure 8, the logical formula.

Although I don't feel the need for calculation instructions, they are extremely common in actual plants. For example, if you want to determine whether the temperature is above or below using the input condition collection command group 302 and branch condition collection command group 31, compare the analog value with the numerical value and use the resulting bit information. There may be cases where it is necessary to perform addition, subtraction, multiplication, division, or more advanced operations in a certain step, but it is clear that such requests can be easily met with the nine examples shown in the present invention.

Further, in the embodiment described above, an example was explained in which instructions are organically connected using an akimulator, but another method such as a stack may be used, and the same effects as in the embodiment described above can be obtained.

Further, similar effects can be obtained even if the instructions are further divided or combined.

〔Effect of the invention〕

As described above, according to the present invention, the sequence controller is configured to include an input condition collection instruction group, a branch condition collection instruction group, an output instruction group, etc. so that logical expressions and arithmetic expressions can be entered in the sequence table. This has the advantage that complex control processing operations can be created using sequence tables.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a sequence table included in a sequence controller according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the instruction table of FIG. 1, FIG. 3 is an operation flowchart of a group of output instructions, and FIG. A sequence table diagram of a conventional sequence controller, FIG. 5 is a diagram of a conventional table execution command, FIG. 6 is a diagram of a conventional fixed data table, FIG. 7 is a 70-chart of a conventional table execution command, and FIG.
The figure is a system configuration diagram including a general sequence controller, Figure 9 is a diagram of commonly used detailed data, and Figure 1
0 is a variable data table diagram of the sequence controller, and FIG. 11 is a detailed status flag diagram. In the figure, 1 is a sequence controller, 30 is a group of input condition collection instructions, 31 is a group of branch condition collection instructions, and 32 is a group of output instructions. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation

Claims (1)

[Claims] In a sequence controller that executes programmable sequence operations written in a sequence table, the sequence table includes a group of input condition collection instructions that collect input data and set them in a data area, and a group of input condition collection instructions that collect input data and set them in a data area, and a group of input condition collection instructions that collect input data and set them in a data area. It has a branch condition collection instruction group that collects instructions to be transferred to the area, a table instruction that inspects the data in the data area, and an output instruction group that collects instructions that output the data in the fixed data area in the sequence table. A sequence controller comprising a data area and a combining means having a data area and an area for combining data when each of the instructions is executed.