JPH02267635A - System check point/restart processing system - Google Patents

Abstract

PURPOSE:To shift the control to a CPU that carried out a check point process by recovering the processing state of the CPU at the relevant time point based on the check point process state stored in an external storage. CONSTITUTION:In a check point process, a system check point/restart processing part 2a stores the process states of the CPU 3 and 4 in an external storage 6. Then the control is given to the CPUs in the check point process by reference to the process state stored in the storage 6 at start. Thus the process states of both CPU 3 and 4 are recovered at a check point. As a result, the control can be shifted to the CPU that carried out a check point process for a data processor consisting of plural CPUs even if an IPL is carried out through an optional CPU at restart. Furthermore the CPU constitution can be recovered at a check point.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a restart process for performing checkpoint processing and restoring the system state at the next system initialization in a pig processing device having a plurality of central processing units. The present invention relates to a system checkpoint/restart processing method.

[Conventional technology]

Conventionally, in this type of system checkpoint/restart processing method, it has been necessary to use the main CPU (central processing unit) to perform checkpoint processing and to perform restart IPL (initial program load) using the main CPU. FIG. 7 is a block diagram showing the configuration of such a conventional system checkpoint/restart processing method.

Referring to FIG. 7, the conventional system checkpoint/restart processing method consists of a system console 1, a system checkpoint/restart processing section 2, and a CP
It is composed of a CPU (A) 3, a CPU (B) 4, a main storage device 5, and an external storage device 6. Here, CPU (A
)3 is the main CPU, and only this CPU (A)3 can perform checkpoint processing and can also start restart IPL. The system checkpoint/restart processing unit 2 is comprised of a checkpoint means 2I, a system stop means 22, a system start means 23, and a restart means 24. The main storage device 5 stores information necessary for data processing.
The external storage device 6 stores the state of the main storage device 5 (CPU state) at any point in time during data processing.

FIG. 8 is a flowchart showing the operation of the checkpoint means 21 shown in FIG. Referring to FIG. 8, the checkpoint means 21 has the functions of a main memory storage step 211 and a system stop means activation step 212.

FIG. 9 is a flowchart showing the operation of the system stop means 22 shown in FIG. 7. Referring to FIG. 9, the system stop means 22 has the function of a system stop step 221.

FIG. 10 shows the operation of the system starting means 23 shown in FIG. 7. Referring to FIG. 10, the system startup means 23 has the functions of a system startup step 231 and a restart means startup step 232.

FIG. 11 is a flowchart showing the operation of the restart means 24 shown in FIG. Referring to FIG. 11, the restart means 24 has the function of a main memory restoration step 241.

Next, the operation will be explained.

The checkpoint means 21 starts operating according to an instruction from the system console 1. Checkpoint means 2
1, in the main memory saving step 211, the CPU
(A) Under the control of step 3, the memory contents of the main storage device 5 are saved in the external storage device 6, and the system stopping means 22 is started in a system stopping means starting step 212. The system stopping means 22 stops the system in a system stopping step 221.

In response to an instruction from the system console 1, the system startup means 23 starts operating. In the system startup means 23,
At system startup step 231, CPU (A)3
starts up the system (IPL) and starts the restart means 24 in a restart means start step 232.

The restart means 24 restores the memory contents from the external storage device 6 to the main storage device 5 under the control of the CPU (A) 3 in a main storage restoration step 241 .

[Problem to be solved by the invention]

In the conventional system checkpoint/restart processing method described above, it is assumed that the main CPU performs the checkpoint, so any CPU can perform the checkpoint process, and furthermore, any CPU can perform the IPL. There was a problem in that it could not be applied to a data processing device with a multi-CPU configuration that can perform the above-mentioned processing.

This invention was made to solve the above problems, and in a data processing device with a multi-CPU configuration, even if an IPL is performed from any CPU at the time of restart, control is not given to the CPU that performed checkpoint processing. It is an object of the present invention to provide a system checkpoint/restart processing method that can be used to restore the CPU configuration at the time of the checkpoint.

[Means to solve the problem]

The system checkpoint/restart processing unit 2a in the system checkpoint/restart processing method according to the present invention saves the processing state of each central processing unit 3.4 in the external storage device 6 during checkpoint processing,
The present invention is characterized in that the central processing unit at the time of checkpoint processing is given control based on the processing state at the time of restart, and the restart processing is performed to restore the processing state of each central processing unit 3 and 4 at the time of checkpoint. Patented O [Operation] During checkpoint processing, the processing status (CPU configuration information) of each central processing unit 3, 4 is saved in the external storage device 6 by the system checkpoint/restart processing section 2a. At the time of restart, the processing state stored in the external storage device 6 is referred to, and control is given to the central processing unit at the time of checkpoint processing based on the processing state, and each central processing unit 3 at the time of checkpoint processing is given control. , 4 is restored.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the configuration of a system checkpoint/restart processing method according to an embodiment of the present invention. Referring to FIG. 1, the embodiment of the present invention includes a system console 1, a system checkpoint/restart processing unit 2a, a CPU (A) 3, a CPU (B)
4, a main storage device 5, and an external storage device 6. Here, CPU (A) 3 and CPU (B) 4 are
Both CPUs can perform checkpoint processing and can also start Lister MPL, so they have completely equal capabilities. The system checkpoint/restart processing section 2a includes a CPU information storage means 25, a checkpoint means 21, and a system stop means 22.
, system startup means 26 , and CPU information restoration means 30
The CPU fixing means 27 and the restart means 28, and the CPU
It is composed of an information restoring means 30 and a CPU state restoring means 29. The external storage device 6 is composed of a CPU information storage section 61 and a main memory storage section 62.

Note that details of the constituent elements will be described later.

Feature 9 of the above embodiment is that the CPU information storage unit 61 stores CPU information at the time of checkpoint, that is, the address of the CPU that performed checkpoint processing, and all CPUs.
This is an external storage area for storing processing states such as the configuration of the PU and control information of each CPU. Further, the CPU information storage means 25 is for fixing the control CPU to one at the time of a checkpoint and storing the CPU information in the CPU information storage section 61. Further, the CPU information restoring means 30 restores the CPU information of the CPU information storage section 61 at the time of restart.
This is for referring to the U information, giving control to the checkpoint CPU based on the information, and restoring the processing state of each CPU at the time of the checkpoint after main memory restoration is completed.

FIG. 2 is a flowchart showing the operation of the CPU information storage means 25 in FIG. Referring to FIG. 2, the CPU information storage means 25 includes a control CPU fixing step 251 and a C
It has a PU information storage step 252 and a checkpoint means activation step 253.

FIG. 3 is a flowchart showing the operation of the system startup means 26 in FIG. Referring to FIG. 3, the system starting means 26 has a system starting step 261 and a CPU fixing means starting step 262.

FIG. 4 is a flowchart showing the operation of the CPU fixing means 27 shown in FIG. Referring to FIG. 4, CPU fixing means 2
7 has a control-CPU determination step 271, a control CPU fixing step 272, and a restart means activation step 273.

FIG. 5 is a flowchart showing the operation of the restart means 28 shown in FIG. Referring to FIG. 5, restart means 2
8 has a main memory restoration step 281 and a CPU state restoration means activation step 282.

FIG. 6 is a flowchart showing the operation of the CPU state restoring means 29 shown in FIG. Referring to FIG. 6, the CPU state restoring means 29 has a CPU state restoring step 291.

Next, the operation of this embodiment will be explained with reference to the drawings.

The CPU information storage means 21 starts operating in response to an instruction from the system console 1. The CPU information storage means 25 determines the CPU that performs the checkpoint in the control CPU fixing step 251, puts other CPUs in a waiting state, and stores the CPU (
A) 3 and CPU (B) CPU information (processing status) of 4
is stored in the CPU information storage section 61 of the external storage device 6, and the checkpoint means 21 is activated in a checkpoint means activation step 253. In the checkpoint means 21, all the contents of the main memory 5 are saved in the main memory storage section 62 of the external storage device 6 in a main memory saving step 211, and the system stopping means 22 is started in a system stopping means starting step 212. The system stop means 22 stops the system in a system stop step 221.

The system starting means 26 starts operating in response to an instruction from the system console 1. In the system starting means 26,
At system startup step 261, CPU (A)3
or CPU (B) 4 starts the system, and in CPU fixing means starting step 262, C
Activate the PU fixing means 27. In the CPU fixing means 27, in the control CPU determination step 271, the external storage device 6
It is determined which CPU was the CPU that performed the checkpoint from the information obtained from the CPU information storage unit 61 of
is fixed as the control CPU, other CPUs are brought into a holding state, and the restart means 28 is started in a restart means starting step 273. The restart means 28 obtains the main memory at the time of the checkpoint from the main memory storage unit 62 of the external storage device 6 in the main memory restoration step 281 and restores it to the main storage device 5, and in the CPU state restoration means activation step 282 In this step, the CPU state restoring means 29 is activated. CPU (A) after getting CPU status CPUI information
The CPU states (processing states) of CPU (B) 3 and CPU (B) 4 are restored.

Note that although the above example shows the case of two CPtJs, if the CPU information of all CPUs is saved, the number of CPUs can be reduced to three.
You may provide more than one.

〔Effect of the invention〕

As described above, according to the present invention, the processing state of each central processing unit is saved in an external storage device during checkpoint processing,
At the time of restart, the central processing unit at the time of checkpoint processing is given control based on its processing state, and the restart processing is performed to restore the processing state of each central processing unit at the time of checkpoint. In a data processing device having a processing unit, even if an IPL is performed from any central processing unit at the time of restart, control can be passed to the central processing unit that performed the checkpoint processing, and the configuration of the central processing unit at the time of the checkpoint can be further improved. can be restored,
Therefore, it is possible to perform checkpoint processing using any central processing unit, and the restart IPL can be performed using any central processing unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a system checkpoint/restart processing method according to an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the CPU information storage means in FIG. 1, and FIG. FIG. 4 is a flowchart showing the operation of the system startup means in FIG. 1, and FIG.
5 is a flowchart showing the operation of the restarting means in FIG. 1; FIG. 6 is a flowchart showing the operation of the CPU state restoring means in FIG. 1; and FIG. 7 is a flowchart showing the operation of the CPU state restoring means in FIG. 1.・A block diagram showing the configuration of the checkpoint/restart processing method; FIG. 8 is a flowchart showing the operation of the checkpoint means in FIG. 7; FIG. 9 is a flowchart showing the operation of the system stop means in FIG. 7; FIG. 10 is a flowchart showing the operation of the system starting means in FIG. 7, and FIG. 11 is a flowchart showing the operation of the restarting means in FIG. 2a... System checkpoint/restart processing unit 1.3, 4... Central processing unit, 5... Main storage device, 6... External storage device, 25... CPU information storage means, 30...CPU information restoration means, 61...CP
U information storage unit. Agent Masu Oiwa! (2 others) Figure No. Book (voluntary) 1990 G Contents of amendment (]) Specification, page 10, line 15 "Information storage means 21"
The text has been corrected to read "information storage means 25." 2. Invention title system/checkpoint restart processing method 3. Relationship with the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Representative of Mitsubishi Electric Corporation Moriya Shiki 4, agent address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo

Claims (1)

[Claims] A plurality of central processing units that perform calculations and controls necessary for data processing, a main memory that stores information necessary for data processing, and an external storage that saves the state of the main memory at any point in time during data processing. , Performs checkpoint processing to save the state of the main storage device in the external storage device based on a command from a predetermined one of the plurality of central processing units, and also saves the state at the next system initialization. In a data processing device equipped with a system checkpoint/restart processing unit that performs restart processing to restore the system, the system checkpoint/restart processing unit is configured to check the processing status of each central processing unit during checkpoint processing. is stored in the external storage device, the central processing unit at the time of the checkpoint process is given control based on the processing state at the time of restart, and the processing state of each central processing unit at the time of the checkpoint is restored. A system that is characterized by
Checkpoint/restart processing method.