JPH02267795A - Digital controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a digital control device that utilizes a multi-port storage element that can be accessed by a plurality of logic operation elements.

[Prior Art] Dual port RAM and the like are conventionally known as multi-port storage elements that can be accessed by a plurality of logic operation elements. These multi-port storage elements (Table) When the same address is accessed from multiple logical operation elements,
It has a function of writing or reading information according to the access order.

Therefore, there are many cases in which it is used in a so-called multi-CPU system that includes a plurality of logic operation elements E. For example, there are many information sources that randomly generate information, and in systems that input information from these sources and process the input information, it is used as follows.

Every time information is generated from a large number of information sources, input processing is performed to input that information (table), which reduces the information processing speed that the logical operation element (hereinafter simply referred to as the CPU) should normally perform. Therefore, multiple CPUs are provided, and the - CPU is in charge of inputting information, and writes the input information by accessing a predetermined address of the dual port RAM.The other CPUs are in charge of information processing, and store the necessary information. The information is read from the dual-port RAM by accessing the address in the dual-port RAM as appropriate.In addition, when it is necessary to initialize the dual-port RAM in such a system (see above), the CPU responsible for inputting information erases the memory contents. Alternatively, processing such as writing a predetermined initial value is executed.

[Problems to be Solved by the Invention] However, systems that effectively utilize the characteristics of multi-port storage elements such as the dual-port RAM described above for the purpose of improving processing speed are known, but they have the following problems. is unresolved.

As information digitization progresses, the amount of information managed by CPUs increases, and the storage capacity of multi-port storage elements, including ordinary RAM, has become extremely large.

This increase in the capacity of multi-port memory elements (on the other hand, increases the time required for initialization, resulting in decreased responsiveness during system startup and reset. The plurality of CPUs using the multi-port storage element are controlled to be in a standby state until the initialization of the multi-port storage element is completed.

As a result, the entire system remains inoperable until the initialization of the multi-port storage elements is completed, which is contrary to the main purpose of multi-CPUs, which is to improve operating speed.

The present invention has been made to solve the above problems, and it is possible to highly efficiently control a system equipped with a plurality of logical operation elements and a plurality of port storage elements, and to make full use of its capabilities.
It is an object of the present invention to provide a digital control device that can quickly complete the initialization of a multi-port storage element even if its capacity increases, and can further improve processing speed and responsiveness.

[Means for Solving the Problems] As shown in FIG. 1, the configuration of the digital control device of the present invention made to achieve the above object includes a plurality of logic operation elements C1, and a plurality of logic operation elements C1. ] A digital control device comprising a multi-port storage element C2 that has an address that can be accessed from a plurality of ports and writes or reads information in accordance with the order of access to the address, wherein the plurality of logical operation elements C1 are The gist of the invention is that, when it becomes necessary to initialize the port storage element C2, a divisional initialization means C1a is provided which initializes the storage area of the multi-port storage element C2 allocated to each logic operation element C]. It is said that

[Function] A plurality of logic operation elements C1+i in the digital control device of the present invention. Division initialization means C1a having the following function.
It is equipped with

Division initialization means C1a and 1 above multi-port storage element C2
The multi-port storage element C2 starts operating when it becomes necessary to initialize the multi-port storage element C2 assigned to each logical operation element C1.
Initialize the storage area.

In other words, the initialization of the multi-port storage element C2 is performed in a shared manner by the plurality of logical operation elements C1. is executed reliably as before.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the present invention more specifically, one embodiment of the present invention will be described below with reference to the drawings.

[Embodiment] The block diagram in FIG. 2 (top) is an example in which an engine control system for controlling an internal combustion engine mounted on a vehicle is constructed using a digital control device that is an embodiment of the present invention.

As shown in the figure, the engine control system of this embodiment
The system uses two CPUs, which are logical operation elements.

The first CPLJIO is in charge of fuel injection control, and inputs various sensor signals and switch signals including engine rotation signals, intake air amount, etc. via input buffers 12 and 14. The input information 1 is subjected to various processes by the CPU 10 according to the program stored in the ROM 16. The storage area required for processing this information is allocated to a predetermined area of the dual-port RAM 18, which is a type of multi-board storage element. Also, the storage area required for the processing of the second CPU 30, which will be described later, is
This dual port RA also handles information that should be shared.
It is written in a predetermined area of M18.

CPU 10 +1 When the various control amounts required for fuel injection control are calculated as the execution result of the above program, the results are sent to the corresponding equipment on the vehicle as a fuel injection control signal and an actuator control signal via the output buffer 20.22. Output as .

The second CPU 30ft is a logic operation element in charge of engine ignition timing, idle speed control, etc.

Therefore, the second CPU 30 (t, rotation signal,
Various switch signals such as an idle switch signal and knocking signals are inputted via input buffers 32 and 34,
It processes it based on a program stored in the ROM 36, and outputs the ignition control signal, idle speed control signal, and actuator control signal that are the results of the processing to predetermined equipment via the output buffer 38.40e. The dual port RAM 18, which is the same as the first CPIJIO described above, is used as a storage area for information necessary for such a series of processing by the CPIJ30.

Note that two signal lines W are indicated by dotted lines in FIG.

x (1) This is unrelated to the configuration of this embodiment, and will be explained again in other embodiments to be described later.

In the engine control system configured as described above, the ROMs 16 and 36 store known fuel injection control programs, ignition timing control programs, etc., and the first CPU 10 and the second CPU 30 store these programs. By executing the control program, the in-vehicle engine can always maintain an optimal state and continue outputting the target torque. Various control methods for such general control are already known, and since the same control as the conventional one is adopted in this embodiment, a detailed explanation thereof will be omitted.

Furthermore, the engine control system I of this embodiment
-L ROM16. An "initialization processing program" is stored in 36, and is executed by the first CPU10 and the second CPU30 at the time of system startup and system reset.

FIGS. 3A and 3B are flowcharts of the "initialization processing program".

First, the initialization processing program (FIG. 3(A)) executed by the first CPU 10 will be explained. This program is stored in the ROM 16 and is sent to the first CPU 10 when the engine control system is started or when it is necessary to reset the system.
The bills loaded will be processed.

When you start processing according to the initialization processing program,
First CPtJloti Dual Photo RAM
18 D address is cleared to erase the information stored there (step 100).

Here, address D is an address of the dual port RAM 18, and is set in the following area.

FIG. 4 is a memory map that visually represents the storage area of the dual port RAM 18 as a linear space.

As shown in the figure, in the initialization processing program (upper
The storage areas of dual port RAM 18 are A, B,
It is recognized by dividing it into three areas: C. Here, area C and table 1 are areas in which information for which initialization processing of storage contents is unnecessary or inappropriate is stored, and are non-initialized areas that are excluded from initialization processing. It is provided in the non-initialization processing area C next to the above-mentioned address D. Note that storage areas A and B are initialization areas that are subject to initialization processing, and this area requires initialization processing. information is stored.

After completing the clearing of address D, the first CPU 10 initializes peripheral circuits such as internal registers, input and output buffers (step 110).

Next, the first CPLJ 10 executes an initialization process to the initialization area of the dual port RAM 8 shown in FIG. 4 (step 120). When the initialization to this initialization area is completed, a flag indicating this is set at address D cleared in step 100 (step 1
30).

When these initialization processes are completed, the first CPUIO determines the memory contents of the address E existing in the non-initialized area C shown in FIG. It is determined whether or not the predetermined time has elapsed (step 150), and the confirmation of the stored contents at address E is repeated until the predetermined time has elapsed. Then, when the memory contents at address E are no longer in a clear state, or when a predetermined period of time has elapsed, the initialization processing program is terminated and the 80
The routine moves to execution of the normal control program stored in M16.

FIG. 3(B) 11 is a flowchart of the initialization processing program executed by the second CPU 30, and its contents are almost the same as that shown in FIG. 3(A). The only difference is the storage area and the address where the flag is set. A brief explanation will be given below.

When the initialization processing program starts, the CPU
30 It, clear the dual port RAM 18 (7) E address (Step 200), and initialize peripheral circuits such as internal registers, input and output buffers (Step 2] 0). Next, the dual port RAM shown in Figure 4
Step 2: Execute the initialization process for initialization area B of
20), step 200 to indicate that initialization is complete.
Set a flag at address E cleared by . (Step 230).

When these initialization processes are completed, the first CPU 10 determines the memory contents of address D, where a flag indicating completion of initialization is set (step 240), until the flag is set or at a predetermined time. After waiting until the time has elapsed (step 250), the initialization processing program is terminated and execution of the normal control program stored in the ROM 36 is started.

The engine control system configured as described above has the following effects.

The above system is a multi-CPU system in which information processing is executed simultaneously and in parallel by the first CPU 10 and the second CPU 30. For this, each CPU l0,30
The control processing executed by the system is extremely fast, making it ideal for engine control systems that require high-speed response.

In addition, since the Dual Port RAMI 8 is shared, there is only one area for storing information to be shared.
Storage capacity is effectively utilized and system simplification is achieved.

Furthermore, in addition to the above effects, since the system is configured to execute the initialization processing program (Figure 3), the dual port RAM is
18 is instantaneously executed, allowing a high-speed transition to control processing.

That is, the initialization area (A
Even if +B) has a large storage capacity, two CPUs
Since the initialization process is executed in a shared manner by l0 and 30, the initialization process is completed in half the time normally required.

In addition, the initialization of the initialization areas A and B of the shared dual port RAM 18 is completed (the other non-initialization area C
This can be easily confirmed by the other CPU 10 or 30 by checking the flag set state of address E. For this reason, dual port R
This avoids the problem of the system starting control before the AM18 initialization process is completed, resulting in a highly reliable system.

Furthermore, if a malfunction occurs in one of the CPUs 10 or 30, initialization of either the initialization area A or B of the dual port RAM 18 becomes impossible. but,
In this case as well, since the normal control is configured to wait for the elapse of a predetermined period of time before transitioning to normal control, the influence on engine control can be minimized.

As is clear from FIG. 4, in the above embodiment, the initialization areas A and B of the dual port RAM 18 handled by the first CPU 10 and the second CPU 30 divide the area requiring initialization into approximately two equal parts. is set. This configuration was made on the premise that the processing capabilities of the +1 CPU 10 and the CPtJ 30 are equivalent. Therefore, when there is a difference in processing capacity between these CPUs (see table), it is important to allocate the initialization area according to the processing capacity and take care to ensure that the initialization processing of both CPUs is completed almost simultaneously. This is preferable in terms of speeding up.

Further, in the above embodiment, a dual port RAM 18 is used as a multi-port storage element, and two CPUs 10 and 30 are used as logical operation elements. However, as can be easily understood, the number of logic operation elements used and the number of ports of a multi-port storage element may be any number greater than or equal to 3, and in that case, the initialization area of the multi-port storage element may be set to a larger number. By assigning the load to the logic operation elements of , the speed of the - layer can be increased. Even in such a case, the allocation of the initialization area is determined according to the processing capacity of the logic operation element,
It is preferable that each logic operation element completes its initialization process at approximately the same time.

Next, another embodiment in which initialization processing is shared by a plurality of CPUs will be described with reference to the first embodiment described above.

In the first embodiment, a non-initialized area C exists in the storage area of the dual port RAM 18, and by using addresses D and E in this area for setting flags, two CPUs l0.
However, dual port RAM 1 can manage the execution state of initialization processing by the other CPLJ.
8 storage areas are required as the initialization area, and the flag setting area may not be able to be secured. The second embodiment (above) takes such a case into consideration.

The hardware configuration of the second embodiment is essentially the same as the first embodiment, and the only difference is the addition of signal lines w and x indicated by dotted lines in the block diagram of the first embodiment (Figure 2). be.

The signal lines w, set to input,
The CPU 30 needs to set W as an input and X as an output. Using these signal lines w and x, a voltage level is sent from the own output port to the input port of the other CPU via the signal line W or It is something to convey. That is, this signal line is connected to D in the first embodiment.
By using address i1 as address E, the same effect as described above can be achieved.

Furthermore, with this configuration, +f, the entire storage area of the dual port RAM 18 can be effectively used as an initialization area.

Furthermore, the operating speed of dual port RAM 18 is generally +
i CPU 10. The operation speed is low compared to the operation speed of logic operation elements such as 30. However, due to the configuration of the first embodiment, such a low-speed dual port RAM
Flag information is exchanged directly between the two CPUs without intervening 18.

Therefore, it is possible to further reduce the time required to write and confirm the flag information, and further speed up the initialization process can be achieved.

[Effect of the invention] As explained above, the digital control device (table 1) of the present invention
When it becomes necessary to initialize the multi-port storage element, the division initialization means is activated to divide the storage area of the multi-port storage element for each logic operation element and execute initialization processing.

Therefore, the initialization process of the multi-port storage element can be completed in a short time, and the responsiveness of the system can be further improved. Therefore, it is possible to maximize the advantages of a system using a plurality of logical operation elements and a plurality of port storage elements, and it is possible to construct an optimal system for applications requiring high-speed response. Further, even if the capacity of the multi-port storage element increases, its initialization can be completed quickly, and processing speed and responsiveness can be maintained above a certain level.

[Brief explanation of drawings]

Fig. 1 shows the basic configuration of the present invention. Fig. 2 shows an example of an engine constructed by installing digital control.
The control system blocks are shown in Figure 3 (A).
(B) is a flowchart of the initialization processing program processed by the same embodiment, and FIG. 4 shows a memo map of the dual port RAM of the same embodiment. 10...First CPU 30...Second CPU1
2, 14, 32. 34...Input buffer 16.3
6...ROM] 8...Dual port RAM

Claims (1)

[Claims] A multi-port storage element that has a plurality of logic operation elements and an address that can be accessed by the plurality of logic operation elements, and that writes or reads information in accordance with the order of access to the addresses. , When the plurality of logic operation elements needs to initialize the multi-port storage element, the plurality of logic operation elements initialize the storage area of the multi-port storage element allocated to each logic operation element. A digital control device characterized by comprising division initialization means for dividing.