JPH04117697A - Multiport memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-port memory circuit, and particularly to a multi-port memory circuit that can realize an improvement in utilization rate.

[Conventional technology]

In recent years, there has been an increasing demand for advanced functions and performance of information processing systems, and there is a growing trend to implement the functions required for the entire system using a multiprocessor system that adopts a functional distribution method. This means that multiple microprocessors (hereinafter referred to as
In this system, a subsystem is formed for each MPU to improve system availability. Along with this, there is an increasing demand for multi-port memories that transmit information between MPUs.

FIG. 3 is a circuit diagram showing a conventional multi-port memory circuit in which data transfer between multiple MPUs is configured using the most common general-purpose multi-port memory.
11 is a shared memory area, and 11 is M which can access the shared memory area 13 independently from the A port via the path line A.
PUA, t2 is connected to shared memory area 1 via pass line B.
3 is an MPUB that can be accessed independently from the B boat, 3
1 is memory area 1 where MPUA 11 and MPU 112 coexist
This is a boat arbitration function that performs access port arbitration only when the same location of 3 is selected, and gives access priority only to the port that arrives first.

Next, the operation will be explained.

Access boats A and B have independent path lines A and B, respectively, and have respective corresponding MPUA I and MP lines.
In response to the operation command from U, 12, the shared memory area 1
Request access to 3.

In this case, MPUA11 connected to A and B boats
, MPUel 2 arbitrarily select addresses of the shared memory area 13 independently and asynchronously, and write and read data from each access port to the arbitrarily selected addresses of the shared memory area 13.

Also, MPUA 11. If the MPU 5 12 selects the same location in the shared memory area 13 in conflict, the boat arbitration function 31, which is an access boat arbitration function, is activated to give access priority to either access port A or B. work. In this case, priority is usually given to the boat that accesses the shared memory area 13 first, and the operation of the MPU of the later arriving boat is temporarily suspended during the address conflict selection period. A Busy signal for (stopping) is output.

In this way, since MPUA 11 and MPUB 12 can be accessed independently and asynchronously via access ports A and B, there is a possibility that the same location in shared memory cell 13 will be competitively selected depending on the address settings from ports A and B. In this case, the following four basic operations are possible depending on the access mode settings from boats A and B.

(1) A port - read B boat - read 2) A port - read B boat - write (3) A
Port - Write B Boat - Read 4) A Boat - Write B Boat - Write In other words, A to the same location as in (1).

If the B port or each is operating in read mode,
Correct data is read to both sides and no particular problem occurs, but if the A and B ports operate in different modes as in (21, (31), the write is performed correctly, but
Within the same cycle period, read data at the opposite port may read data before the write operation, read data after the write operation, or read unstable data just during the write operation, depending on the data read point. Possibilities etc. arise.

Furthermore, when the A and B ports perform a write operation as in (4), there is a possibility that opposite data will be written to each other, making the memory contents uncertain.

[Problem to be solved by the invention]

Conventional multi-port memory circuits are configured as described above, so when the same address in the shared memory is competitively selected, the priority of access ports must be arbitrated using the boat arbitration function. Due to the arbitration function, the MPU side that has determined that the request to access the shared memory has arrived later has to wait in a wait state only during the address conflict selection period, which is a problem in that the operating rate of the entire system decreases. there were.

The second invention was made to solve the above problem, and it is not necessary to wait (stop) the operation of the MPU when selecting a shared memory conflict, which improves the utilization rate of the MPU. The purpose is to obtain a multi-port memory circuit.

[Means to solve the problem]

In the multi-port memory circuit according to the present invention, a shared memory cell area is divided into a plurality of banks, and access ports for writing and reading to each of the shared memory cell areas are fixed.

[Effect]

In this invention, the shared memory cell area is divided into a plurality of banks, and access ports for writing and reading to each of the shared memory cell areas are fixed, so a boat arbitration function for access boat arbitration is provided. This eliminates the need for a wait request output signal to the MPU, thereby reducing the number of terminals, and since no wait state occurs in the MPU, the operating rate of the MPU itself can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a multi-port memory circuit according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. A first shared memory area 15 performs only read operations from the B port, and a second shared memory area 15 performs only read operations from the A port, and only write operations from the B port.

Further, FIG. 2 is a circuit diagram specifically showing the configuration diagram shown in FIG. A first shared memory cell area that only writes from the boat and only reads from the B boat; 23 is a shared memory area 21 that only reads from the A boat;
The second coexisting memory cell area 24 is for writing only from the B port, and in order to enable independent and asynchronous reading and writing from the access ports A and B, one address line and two data lines are connected to the second coexisting memory cell area 24. 25 is a data write control circuit from the A boat, 26 is a data read control circuit to the B boat, 2
7 is a data read control circuit to the A port, and 28 is a data write control circuit from the B port.

Next, the operation will be explained.

As shown in Figure 2, A is a shared memory area 2 that can be independently and asynchronously written and read from 82 ports.
1, the data write control circuit 25.1 of the A boat responds to the write and read requests of the MPUs of the A and B boats. B boat data write control circuit 28. A
Boat data read control circuit 26. Any two of the data read control circuits 27 of the B boat act;
A data write or read operation is performed on the memory cell selected by the address line of each boat. However, the data write control circuit and data read control circuit of the same boat are not turned on at the same time.

In this case, the following four basic operations can be considered depending on the access mode settings from both boats.

(1) A boat - Readout B boat - Readout 2)
Port A - Read B Hold - Write (3) A Boat - Write B Boat - Read 4) A Boat - Write B Hold - Write Among the above four basic operations, (as shown in 11, both A and B ports read) , or when the same instruction is executed such as writing on both A and B boats as in (4), the same address will not be selected. In particular, as in (4), when both A and B boats write, the same address will not be selected. Since the same location in the shared memory is not selected even when accessed with In this case, there is a possibility that addresses from A and B boats will be competitively selected, and the boat output data during the read operation may change during the same cycle due to the write operation of the opposite boat. This can be avoided by reading the output data twice on the software and determining whether the data is final.

As described above, according to this embodiment, the shared memory cell area is divided into a plurality of banks, and the write and read access ports for each of the shared memory cell areas are fixed, so that the same location in the shared memory is not competitively selected. There is no need to temporarily stop the operation of one of the MPUs when a problem occurs, and the operating rate of the MPU can be improved.

In the above embodiment, the shared memory area 21 is the first memory area 22 that performs only write operations from the A port and only read operations from the B port, only read operations from the A port, and only write operations from the B port. By dividing the memory area into a second memory area 23 that performs In addition, a function for reading written data may be added to the write operation board itself, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the multi-port memory circuit of the present invention, the shared memory cell area is divided into a plurality of banks, and the access ports for writing and reading to each of the shared memory cell areas are fixed. It is no longer necessary to temporarily stop the operation of one MPU when a conflicting address is selected, improving the MPU utilization rate, and eliminating the need for a port arbitration function for access boat arbitration. Accordingly, the wait request output signal to the MPU can also be omitted, which has the effect of reducing the number of terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a 2-point memory circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram specifically showing the 2-point memory circuit of FIG. 1, and FIG. FIG. 2 is a configuration diagram of a typical two-point memory circuit. In the figure, 11 is MPUA, 12 is MPUB, 13 is a shared memory area, 14 is a first shared memory area, 15 is a second shared memory area, 22 is a first shared memory cell area, and 23 is a second shared memory area. A shared memory cell area, 24 a shared memory cell for 1 bit, 25 an A boat data write control circuit, 26 a B boat data read control circuit, 27
28 is a B port data write control circuit, and 31 is a boat arbitration function. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a multi-port memory circuit having two or more access ports and a shared memory cell area that is requested to be accessed by the access ports, a plurality of divided memory areas formed by dividing the shared memory cell area into banks. and means for fixing the access port for writing to and reading from each of the divided memory areas.