JPH0226786B2 - - Google Patents
Info
- Publication number
- JPH0226786B2 JPH0226786B2 JP57068207A JP6820782A JPH0226786B2 JP H0226786 B2 JPH0226786 B2 JP H0226786B2 JP 57068207 A JP57068207 A JP 57068207A JP 6820782 A JP6820782 A JP 6820782A JP H0226786 B2 JPH0226786 B2 JP H0226786B2
- Authority
- JP
- Japan
- Prior art keywords
- brazing
- plated
- lead
- ceramic substrate
- brazed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体用リードピンのろう付方法の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for brazing semiconductor lead pins.
近時、半導体IC或いはLSIは、高信頼性の要請
から従来使用されてきたデユアルイン・パツケー
ジ型のものからプラグイン・パツケージ型のもの
に変わりつつある。 Recently, semiconductor ICs or LSIs are changing from the conventional dual-in package type to the plug-in package type due to the demand for high reliability.
このプラグイン・パツケージIC用リードピン
のセラミツク基板へのろう付は、第１図ａに示す
如くセラミツク１上にメタライズし、次にメタラ
イズ２上にニツケルめつき３を施し、次いでこの
セラミツク基板４のニツケルめつき３上に第１図
ｂに示す如くカーボン治具５を用いてろう材６を
セツトし、次にろう材６の上にリードピン７をセ
ツトし、然る後電気炉中で加熱してろう付する方
法が一般的であつた。 To braze the plug-in package IC lead pins to the ceramic substrate, metallize the ceramic 1 as shown in FIG. A brazing filler metal 6 is set on the nickel plating 3 using a carbon jig 5 as shown in FIG. The common method was to braze.
然し乍ら、このろう付方法では、ろう材６が極
めて小さい為、セラミツク基板４のニツケルめつ
き３上にセツトされないものが出たり、セツトさ
れてもろう材６の位置が悪いとリードピン７のろ
う付強度が低かつたり、ろう付されないなどのろ
う付不良が多かつた。しかもろう付不良を起こし
たセラミツク基板４は処分するか或いはリードピ
ン７を再ろう付しなければならないのであるが、
処分すると製造上セラミツク基板４、リードピン
７の歩留りが極めて悪くなり、リードピン７を再
ろう付すると甚だ手間がかかるので、この点の改
善が要望されていた。 However, in this brazing method, since the brazing material 6 is extremely small, some may not be set on the nickel plating 3 of the ceramic substrate 4, or even if it is set, if the brazing material 6 is in a bad position, the lead pins 7 may not be brazed. There were many brazing defects such as low strength and failure to braze. Moreover, the ceramic substrate 4 that has caused a brazing defect must be disposed of or the lead pins 7 must be re-brazed.
When disposed of, the production yield of the ceramic substrate 4 and lead pins 7 becomes extremely poor, and re-brazing the lead pins 7 takes a lot of effort, so there has been a demand for improvement in this respect.
この為、最近第１工程でリードピン７とろう材
６のみをろう付し、第２工程でこのろう付された
リードピン７を治具を用いてセラミツク基板４の
ニツケルめつき３上にろう付する方法が行われて
いる。この時、第２図ａ，ｂに示すようにろう材
６が正しくろう付されたリードピン７を用いれば
セラミツク基板４にリードピン７を正しくろう付
できるが、第３図に示すようにろう材６がずれて
ろう付されたリードピン７や第４図に示すように
ろう材６がろう付されないリードピン７を用いる
と、セラミツク基板４にリードピン７がろう付さ
れてもろう付強度が弱かつたり、ろう付されなか
つたりするものである。従つて、ろう材６をろう
付したリードピン７の良品を選別する工程が必要
となり、またリードピン７の歩留りが悪かつた。 For this reason, recently, only the lead pin 7 and the brazing material 6 are brazed in the first step, and in the second step, the brazed lead pin 7 is brazed onto the nickel plating 3 of the ceramic substrate 4 using a jig. method is being done. At this time, as shown in FIGS. 2a and 2b, if the lead pin 7 to which the brazing material 6 is properly brazed is used, the lead pin 7 can be properly brazed to the ceramic substrate 4, but as shown in FIG. If a lead pin 7 is soldered with a misalignment or a lead pin 7 to which the brazing material 6 is not soldered as shown in FIG. 4 is used, even if the lead pin 7 is brazed to the ceramic substrate 4, the brazing strength may be weak. It is not soldered and is slick. Therefore, a process of selecting good lead pins 7 to which the brazing filler metal 6 is brazed is required, and the yield of the lead pins 7 is poor.
本発明はかかる諸事情に鑑みなされたもので、
プラグイン・パツケージIC、LSI等の半導体用リ
ードピンを極めて簡便に且つ効率的に歩留り良く
確実にセラミツク基板にろう付するろう付方法を
提供せんとするものである。 The present invention was made in view of these circumstances,
The present invention aims to provide a brazing method for reliably brazing lead pins for semiconductors such as plug-in package ICs and LSIs to ceramic substrates in an extremely simple and efficient manner with a high yield.
本発明による半導体用リードピンのろう付方法
を図によつて説明すると、先ず第５図ａに示す如
く半導体用リードピン７の全面（或いは側面）に
ろう材成分Ａをめつきし、その上にろう材成分Ｂ
をめつきする。このようにして少なくとも２種類
のろう材成分Ａ，Ｂ…を必要に応じ適当な層数と
なるように層状に湿式めつき法によりめつきす
る。然る後このろう材成分Ａ，Ｂ…が層状にめつ
きされたリードピン７′を適当な治具を用いてメ
タライズし、更にニツケルめつきを施されたセラ
ミツク基板４上にセツトし、不活性ガス中又は還
元性ガス中で炉中にて加熱して第５図ｂに示す如
くろう付する。 The method for brazing semiconductor lead pins according to the present invention will be explained with reference to the drawings. First, as shown in FIG. Material component B
to look at. In this way, at least two types of brazing filler metal components A, B, etc. are plated in layers by a wet plating method so as to have an appropriate number of layers as required. Thereafter, the lead pin 7' on which the brazing filler metal components A, B, etc. are plated in layers is metalized using an appropriate jig, and further set on a nickel-plated ceramic substrate 4, and then inert. It is heated in a furnace in a gas or reducing gas and brazed as shown in FIG. 5b.
上記の如くリードピン７の全面（或いは側面）
にめつきすると、リードピン７の表面が滑らかに
なり、セラミツク基板４上に治具を用いてセツト
する際、つまり治具のソケツトに挿入する際、余
分な押入力を必要としないものである。更に詳し
く言えばプラグイン・パツケージ型ICはピンの
数が非常に多いので、一本毎の表面粗さが大きい
と、治具のソケツトへの挿入時に多大な力を必要
とするが、リードピン７の全面（或いは側面）に
めつきすることにより、円滑、容易に挿入され
る。更にリードピン７に用いられているFe−Ni
系合金或いはFe−Ni−Co系合金はろう材に用い
られるAg合金と固溶しないので、溶融したろう
材が適量自重で下部に流下し、セラミツク基板４
とリードピン７との間での毛細現象によりフイレ
ツトが形成され、円滑にろう付が行われるもので
ある。 As mentioned above, the entire surface (or side surface) of the lead pin 7
When plated, the surface of the lead pin 7 becomes smooth, and no extra pushing force is required when setting it on the ceramic substrate 4 using a jig, that is, when inserting it into the socket of the jig. More specifically, since plug-in package type ICs have a very large number of pins, if the surface roughness of each pin is large, a large amount of force is required when inserting the jig into the socket. By plating the entire surface (or side surface) of the holder, it can be inserted smoothly and easily. Furthermore, Fe-Ni used for lead pin 7
Since the Fe-Ni-Co alloy or the Fe-Ni-Co alloy does not form a solid solution with the Ag alloy used for the brazing filler metal, an appropriate amount of the molten brazing filler metal flows down under its own weight and forms the ceramic substrate 4.
A fillet is formed by the capillary phenomenon between the lead pin 7 and the lead pin 7, and brazing is performed smoothly.
また異なるろう材成分を層状にめつきすると、
合金めつきの不可能なろう材であつても、この合
金と同一組成の単一金属を層状にめつきすること
により、合金めつきと同等のろう材を得ることが
できるものである。そしてろう付温度を下げるこ
とができ、フイレツトの広がりを抑えることがで
きて効率の良いろう付が可能となるものである。 Also, when different brazing filler metal components are plated in layers,
Even if a brazing material cannot be plated with an alloy, it is possible to obtain a brazing material equivalent to alloy plating by plating a single metal having the same composition as the alloy in a layered manner. Furthermore, the brazing temperature can be lowered, the spread of the fillet can be suppressed, and efficient brazing can be achieved.
次に本発明の半導体用リードピンのろう付方法
の効果を明瞭ならしめる為に具体的な実施例と従
来例について説明する。 Next, in order to clarify the effects of the semiconductor lead pin brazing method of the present invention, specific embodiments and conventional examples will be described.
実施例 １
Fe−Ni42重量％より成る直径0.4mm、長さ４mm
の20万本のリードピンに、バレルめつきを施し、
Agめつき5μ、更にその上にCuめつき5μを湿式め
つき法により施して全面２層めつきのリードピン
を得た。このリードピンを無差別に50本抜き出
し、これをメタライズし、更にニツケルめつきを
施したセラミツク基板上に治具を用いてセツト
し、900℃、H2雰囲気中のコンベア炉でろう付を
行つた処、ろう付不良は皆無あつた。Example 1 Diameter 0.4 mm, length 4 mm made of Fe-Ni 42% by weight
Barrel plating is applied to 200,000 lead pins,
A lead pin with two layers of plating on the entire surface was obtained by applying 5μ of Ag plating and then 5μ of Cu plating on top of that using a wet plating method. Fifty of these lead pins were randomly extracted, metallized, set on a nickel-plated ceramic substrate using a jig, and brazed in a conveyor furnace at 900°C in an H2 atmosphere. There were no brazing defects.
実施例 ２
Fe−Ni29重量％−Co17重量％より成る直径0.4
mmの線材を作り、この線材にAgめつき8μ、更に
その上にCuめつき2μを湿式めつき法により施し
た後長さ４mm切断して側面にめつきされたリード
ピンを得た。このリードピンを無差別に50本抜き
出し、これをメタライズし、更にニツケルめつき
を施したセラミツク基板上に治具を用いてセツト
し、850℃、H2雰囲気中のコンベア炉でろう付を
行つた処、ろう付不良は皆無であつた。Example 2 Diameter 0.4 consisting of Fe-Ni29% by weight-Co17% by weight
A wire rod with a diameter of 4 mm was made, and the wire was coated with 8 μm of Ag plating and then 2 μm of Cu plating on top of that using a wet plating method, and then cut to a length of 4 mm to obtain a lead pin plated on the side surface. Fifty of these lead pins were randomly extracted, metallized, set on a nickel-plated ceramic substrate using a jig, and brazed in a conveyor furnace at 850°C in an H2 atmosphere. However, there were no brazing defects.
従来例
Fe−Ni42重量％より成る直径0.4mm、長さ４mm
のリードピン100本を、Ag−Cu28重量％より成
る直径0.4mm、長さ0.4mmのろう材を用い、メタラ
イズし更にニツケルめつきを施したセラミツク基
板上に治具を用いてセツトし、850℃、H2雰囲気
中のコンベア炉でろう付を行つた処、ろう付不良
は43本もあつた。Conventional example Made of Fe-Ni 42% by weight, diameter 0.4 mm, length 4 mm
100 lead pins were set using a jig on a ceramic substrate that was metallized and nickel plated using a brazing filler metal made of 28% Ag-Cu with a diameter of 0.4 mm and a length of 0.4 mm, and heated at 850℃. When brazing was performed in a conveyor furnace in an H2 atmosphere, there were 43 brazing defects.
尚、上記実施例は、２種類のろう付成分を２層
にめつきした場合であるが、これは二元合金のろ
う材を作つてリードピンをセラミツク基板上にろ
う付する為で、三元或いは四元合金のろう材を作
つてリードピンをセラミツク基板上にろう付する
場合は、３種類或いは４種類のろう材成分を３層
或いは４層にめつきしても良いものである。 The above example is a case in which two types of brazing components are plated in two layers, but this is because a binary alloy brazing material is made and lead pins are brazed onto a ceramic substrate. Alternatively, when a quaternary alloy brazing material is made and lead pins are brazed onto a ceramic substrate, three or four types of brazing material components may be plated in three or four layers.
また２種類以上のろう材成分を層状にめつきす
る場合においても各ろう材成分は１層のみなら
ず、交互に数層繰り返しめつきしても良いもの
で、これはろう材成分の数と組成によつて適宜選
定するものである。 Also, when plating two or more types of brazing filler metal components in layers, each brazing filler metal component may be plated not only in one layer, but also in several layers alternately, and this depends on the number of brazing filler metal components. It is selected as appropriate depending on the composition.
以上詳記した通り本発明の半導体用リードピン
のろう付方法は、半導体用リードピンの全面又は
側面に少なくとも２種類のろう材成分を層状にめ
つきした後このリードピンをメタライズし更にニ
ツケルめつきを施されたセラミツク基板上にセツ
トし不活性ガス中又は還元性ガス中で炉中ろう付
するのであるから、セラミツク基板へのリードピ
ンとろう材のセツトが極めて簡便となり、またろ
う付も効率的に確実に行われてろう付不良が生じ
ないので、リードピンを処分したり、再ろう付し
たりする必要がなく、リードピンの歩留りが極め
て良好で、生産性の向上に寄与する処大なるもの
がある。 As detailed above, the method for brazing semiconductor lead pins of the present invention involves plating at least two types of brazing material components in layers on the entire surface or side surfaces of a semiconductor lead pin, then metalizing the lead pin, and then applying nickel plating. Since the lead pins and brazing filler metal are set on the ceramic substrate and brazed in a furnace in an inert gas or reducing gas, setting the lead pins and brazing filler metal on the ceramic substrate is extremely simple, and brazing is also efficient and reliable. Since the brazing process is carried out after a long period of time and no brazing defects occur, there is no need to dispose of the lead pins or re-braze them, and the yield of lead pins is extremely good, which greatly contributes to improving productivity.
また本発明の半導体用リードピンのろう付方法
によれば、合金めつきの不可能なろう材であつて
も、この合金と同一組成の単一金属をリードピン
に層状めつきしてセラミツク基板にろう付するこ
とにより合金めつきと同等のろう材でセラミツク
基板にろう付したことになり、しかもろう付温度
が低下し、フイレツトの広がりが抑えられて効率
の良いろう付を行うことができるという効果もあ
る。 Furthermore, according to the method for brazing semiconductor lead pins of the present invention, even if the brazing material cannot be alloyed, a single metal having the same composition as the alloy can be layer-plated onto the lead pin and then brazed to the ceramic substrate. By doing this, the ceramic substrate is brazed with a brazing material equivalent to that used for alloy plating, and the brazing temperature is lowered, which suppresses the spread of the fillet and enables more efficient brazing. be.
第１図ａ，ｂは従来の半導体用リードピンのろ
う付方法の工程を示す図、第２図ａ，ｂはリード
ピンにろう材が正しくろう付された状態を示す
図、第３図はリードピンにろう材がずれてろう付
された状態を示す図、第４図はリードピンにろう
材がろう付されない状態を示す図、第５図ａ，ｂ
は本発明の半導体リードピンのろう付方法の工程
を示す図である。
１……セラミツク、２……メタライズ、３……
ニツケルめつき、４……セラミツク基板、６……
ろう材、７……従来の半導体用リードピン、７′
……本発明のろう付方法に於ける半導体用リード
ピン、Ａ，Ｂ……ろう材成分。
Figures 1a and b are diagrams showing the process of the conventional brazing method for semiconductor lead pins, Figures 2a and b are diagrams showing the state in which the brazing material is correctly brazed to the lead pin, and Figure 3 is a diagram showing the state in which the brazing material is properly brazed to the lead pin. Figure 4 shows a state in which the brazing metal is misaligned and brazed. Figure 4 shows a state in which the solder metal is not brazed to the lead pin. Figures 5 a and b.
FIG. 3 is a diagram showing the steps of the semiconductor lead pin brazing method of the present invention. 1... Ceramic, 2... Metallized, 3...
Nickel plating, 4...ceramic substrate, 6...
Brazing metal, 7... Conventional semiconductor lead pin, 7'
... Lead pin for semiconductor in the brazing method of the present invention, A, B... Brazing material components.
Claims (1)
くとも２種類のろう材成分を層状にめつきし、然
る後このろう材成分が層状にめつきされたリード
ピンを治具を用いてメタライズし更にニツケルめ
つきを施されたセラミツク基板上にセツトし不活
性ガス中又は還元性ガス中で炉中ろう付すること
を特徴とする半導体用リードピンのろう付方法。1. At least two types of brazing filler metal components are plated in a layer on the entire surface or side surface of a semiconductor lead pin, and then the lead pin plated with the layered brazing filler metal component is metalized using a jig and further nickel plated. 1. A method for brazing semiconductor lead pins, which comprises setting the lead pins on a ceramic substrate which has been subjected to the above treatment and brazing the lead pins in a furnace in an inert gas or a reducing gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068207A JPS58184747A (en) | 1982-04-23 | 1982-04-23 | Brazing method of lead pin for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068207A JPS58184747A (en) | 1982-04-23 | 1982-04-23 | Brazing method of lead pin for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58184747A JPS58184747A (en) | 1983-10-28 |
| JPH0226786B2 true JPH0226786B2 (en) | 1990-06-12 |
Family
ID=13367113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57068207A Granted JPS58184747A (en) | 1982-04-23 | 1982-04-23 | Brazing method of lead pin for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184747A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2608287B2 (en) * | 1987-06-12 | 1997-05-07 | イビデン 株式会社 | Graphite jig |
-
1982
- 1982-04-23 JP JP57068207A patent/JPS58184747A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58184747A (en) | 1983-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3986255A (en) | Process for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein | |
| DE69018846T2 (en) | Semiconductor device type ceramic package and method of assembling the same. | |
| US4518112A (en) | Process for controlled braze joining of electronic packaging elements | |
| US4675243A (en) | Ceramic package for semiconductor devices | |
| WO1997018584A1 (en) | Method for forming bump of semiconductor device | |
| US4672739A (en) | Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate | |
| US4755631A (en) | Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate | |
| JPS641060B2 (en) | ||
| JP2001274539A (en) | Electrode joining method for printed wiring board loaded with electronic device | |
| JPH05198697A (en) | Formation of metal via on silicon substrate and fabrication of multi chip module | |
| JPS583962A (en) | Stress free nickel layer formation | |
| JPH0226786B2 (en) | ||
| JPH04263462A (en) | Semiconductor device and manufacture thereof | |
| JPS61196546A (en) | Film carrier integrated circuit and manufacture thereof | |
| JP3470789B2 (en) | Wiring board and method of manufacturing the same | |
| JP3049948B2 (en) | Package manufacturing method | |
| KR900003472B1 (en) | Plating process for an electronic part | |
| JPH05259593A (en) | AlN circuit board | |
| CN110744163B (en) | Heat migration resistant micro welding spot structure and preparation method thereof | |
| JPH0146228B2 (en) | ||
| JPH0214787B2 (en) | ||
| JPH06125162A (en) | Manufacture of ceramic wiring board | |
| JPH0226787B2 (en) | ||
| JPH07120845B2 (en) | Ceramic wiring board and manufacturing method thereof | |
| JPS6286895A (en) | How to solder electronic components |