JPH02267952A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH02267952A JPH02267952A JP8900689A JP8900689A JPH02267952A JP H02267952 A JPH02267952 A JP H02267952A JP 8900689 A JP8900689 A JP 8900689A JP 8900689 A JP8900689 A JP 8900689A JP H02267952 A JPH02267952 A JP H02267952A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulating film
- semiconductor device
- concave
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- -1 nitrogen ions Chemical class 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000010354 integration Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置の製造方法に係り、新らしい誘電体
分離法の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a semiconductor device using a novel dielectric isolation method.
〔従来の技術］
従来、半導体基板の平面状表面から酸素又は窒素イオン
打込みにより平面状に絶縁膜を埋め込ん［発明が解決し
ようとする課題］
しかし、上記従来技術によると必ずしも半導体集積回路
装置の集檀度を向上する事ができないと云う課題が有っ
た。[Prior Art] Conventionally, an insulating film has been buried in a planar shape from the planar surface of a semiconductor substrate by implanting oxygen or nitrogen ions [Problem to be Solved by the Invention] However, the above-mentioned conventional technology does not necessarily solve the problem of integration of semiconductor integrated circuit devices. The problem was that it was not possible to improve the level of enjoyment.
本発明はかかる従来技術の課題を解決し、半導体基板表
面からイオン打ち込みにより絶縁膜を埋め込んで形成す
る方法に関し、新らしい方法を提供する事を目的とする
。It is an object of the present invention to solve the problems of the prior art and to provide a new method for forming an insulating film by embedding it from the surface of a semiconductor substrate by ion implantation.
［課題を解決するための手段］
上記課題を解決するために本発明は、半導体装置の製造
方法に関し、半導体基板表面に凹又は凸形状処理を施し
、該凹又は凸形状処理した半導体基板表面から酸素又は
窒素イオン等の打込み処理を施して、凹又は凸状に絶縁
膜を埋め込んで形成する手段を取る事を基本とする。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device, in which a concave or convex shape treatment is performed on the surface of a semiconductor substrate, and from the surface of the semiconductor substrate subjected to the concave or convex shape treatment. The basic method is to implant an insulating film into a concave or convex shape by implanting oxygen or nitrogen ions.
［実施例］ 以下実施例により本発明を詳述する。[Example] The present invention will be explained in detail with reference to Examples below.
第１図及び第２図は本発明の実施例を示す半導体装置の
要部製造工程での断面図である。FIGS. 1 and 2 are cross-sectional views showing the main parts of a semiconductor device in a manufacturing process according to an embodiment of the present invention.
第１図では、半導体基板１の表面からホト・エツチング
法により溝部４が凹状に形成され、該凹状部を含む表面
から酸素イオン等のイオン打ち込み処理を施して、絶縁
膜２を凹状に半導体膜３を表面に残して埋込んで形成し
て成る。本例の応用としては、例えば溝部４と平面部を
含む表面にゲート酸化膜とゲート電極等を形成してＭＯ
３型ＦＥＴと成し、溝部をトレンチ・キャパシタとして
用いて集積度の向上を計ったり、溝部をトレンチ・ゲー
トとして用いてこれ又集積度の向上を計ったり、更には
溝部４に形成された能動又は非能動素子と平面部に形成
された能動又は非能動素子とを半導体膜６に形成された
拡散層にて繋ぎ、集積度の向上を計ることもできる。In FIG. 1, a groove 4 is formed in a concave shape from the surface of a semiconductor substrate 1 by photo-etching, and an ion implantation process such as oxygen ions is performed from the surface including the concave portion to form an insulating film 2 in a concave semiconductor film. 3 is left on the surface and embedded. As an application of this example, for example, a gate oxide film, a gate electrode, etc. are formed on the surface including the groove portion 4 and the plane portion, and the MO
3-type FET, and the groove can be used as a trench capacitor to improve the degree of integration, or the groove can be used as a trench gate to improve the degree of integration. Alternatively, the degree of integration can be improved by connecting the non-active element and the active or non-active element formed on the plane part through a diffusion layer formed in the semiconductor film 6.
第２図では、半導体基板１１の表面にフィールド絶縁膜
１３を凸状に形成した表面から酸素イオン等を打ち込ん
で、絶縁膜１２を完全誘電体分離形に構成し、誘電体分
離された半導体島１４を形成し、該半導体島１４にはＭ
Ｏ８型ＩＦＫＴ等の能動素子や非能動素子等が誘電体分
離されて高集噴度に形成する事ができる。尚、半導体島
１４が予じめエピタキシャル成長処理によりフィルド絶
縁膜１３の平面と同−平面に迄育成されていても本発明
が適用される事は云うまでもな（、更には、半導体島１
４と成るべきところに予じめ能動素子や非能動素子を形
成して置いてから酸素イオン等のイオン打込み等により
絶縁膜１２等を形成しても′良い事は第１図の実施例共
々云うまでもない。In FIG. 2, a field insulating film 13 is formed in a convex shape on the surface of a semiconductor substrate 11, and oxygen ions are implanted into the surface to form an insulating film 12 completely dielectrically isolated, resulting in dielectrically isolated semiconductor islands. 14, and the semiconductor island 14 has M
Active elements such as O8 type IFKT, non-active elements, etc. can be dielectrically separated and formed with high concentration. It goes without saying that the present invention is applicable even if the semiconductor island 14 has been grown in advance by epitaxial growth processing to the same plane as the plane of the filled insulating film 13 (furthermore, the semiconductor island 14
In the embodiment shown in FIG. 1, it is also possible to form the active elements and inactive elements in advance in the locations where they should be formed, and then form the insulating film 12 by implanting oxygen ions or the like. Needless to say.
［発明の効果］
本発明により半導体基板表面に絶縁膜を埋め込んで形成
する半導体集積回路装置の一層の集積度向上を計る事が
できる効果がある。[Effects of the Invention] The present invention has the effect of further improving the degree of integration of a semiconductor integrated circuit device formed by embedding an insulating film into the surface of a semiconductor substrate.
第１図及び第２図は本発明の実施例を示す半導体装置の
要部製造工程での断面図である。
１．１１・・・・・・・・・半導体基板２．１２・・・
・・・・・・絶縁膜
３・・・・・・・・・・・・・・・・・・半導体膜４・
・・・・・・・・・・・・・・・・・溝部１３・・・・
・・・・・・・・・・・フィルド絶縁膜１４・・・・・
・・・・・・・・・半導体膜島以上FIGS. 1 and 2 are cross-sectional views showing the main parts of a semiconductor device in a manufacturing process according to an embodiment of the present invention. 1.11... Semiconductor substrate 2.12...
...Insulating film 3... Semiconductor film 4.
・・・・・・・・・・・・・・・Groove 13...
......Filled insulating film 14...
・・・・・・More than a semiconductor film island
Claims (1)
は凸形状処理された前記半導体基板表面から酸素又は窒
素イオン打込みにより凹又は凸形状に絶縁膜を埋め込ん
で形成する事を特徴とする半導体装置の製造方法。The semiconductor substrate surface is processed to have a concave or convex shape, and an insulating film is formed by implanting oxygen or nitrogen ions into the concave or convex shape from the concave or convex surface of the semiconductor substrate. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8900689A JPH02267952A (en) | 1989-04-08 | 1989-04-08 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8900689A JPH02267952A (en) | 1989-04-08 | 1989-04-08 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02267952A true JPH02267952A (en) | 1990-11-01 |
Family
ID=13958760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8900689A Pending JPH02267952A (en) | 1989-04-08 | 1989-04-08 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02267952A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372950A (en) * | 1991-05-18 | 1994-12-13 | Samsung Electronics Co., Ltd. | Method for forming isolation regions in a semiconductor memory device |
| JP2007142134A (en) * | 2005-11-18 | 2007-06-07 | Sumco Corp | Manufacturing method of SOI substrate |
-
1989
- 1989-04-08 JP JP8900689A patent/JPH02267952A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372950A (en) * | 1991-05-18 | 1994-12-13 | Samsung Electronics Co., Ltd. | Method for forming isolation regions in a semiconductor memory device |
| JP2007142134A (en) * | 2005-11-18 | 2007-06-07 | Sumco Corp | Manufacturing method of SOI substrate |
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