JPH02267967A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH02267967A
JPH02267967A JP8904489A JP8904489A JPH02267967A JP H02267967 A JPH02267967 A JP H02267967A JP 8904489 A JP8904489 A JP 8904489A JP 8904489 A JP8904489 A JP 8904489A JP H02267967 A JPH02267967 A JP H02267967A
Authority
JP
Japan
Prior art keywords
substrate
film
junction
exposed
mesa groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8904489A
Other languages
Japanese (ja)
Inventor
Kazuyasu Yoneyama
米山 和穏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP8904489A priority Critical patent/JPH02267967A/en
Publication of JPH02267967A publication Critical patent/JPH02267967A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the adhesion of a passivation material to a semiconductor substrate and to make possible the formation of a stable electrode film by a method wherein a substrate surface region which comes into contact to a mesa groove formation region is roughened by sandblasting. CONSTITUTION:The surface of a silicon substrate 1 is covered with a resist film 5, which is used as a maskant, excepting the formation region of a mesa groove 4 and a wet etching is performed. As the edge part of the film 5 coats a sandblasted region 3 of the surface of the substrate 1, the film 5 is closely adhered to the substrate 1 at this region and is never peeled from the substrate 1. As a result of the wet etching, the groove 4 is formed, a p-n junction is exposed on the inner surface of the groove and a junction covering resin 6 which is used as a passivation material is applied on this exposed surface, but as the end part of this resin 6 is also closely adhered to the sandblasted region 3, the resin 6 is never peeled from the inner surface of the groove 4. After that, a metal film is deposited on the exposed surface of the substrate 1. Thereby, the substrate surface is smoothened, the deposited film is closely adhered to the substrate surface and a stable electrode film is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、少なくとも一つのpn接合を有する半導体基
板表面にマスク剤を被着し、マスク剤で覆われない部分
をエツチングしてメサ溝を形成してメサ溝内面にpn接
合を露出させ、露出したpn接合をガラス、ポリイミド
あるいは接合被覆樹脂(JCR)などのパッシベーショ
ン材料でコーティングし、さらに基板表面に金属電極膜
を被着する半導体素子の製造方法に関する。
Detailed Description of the Invention [Industrial Application Field] The present invention involves applying a masking agent to the surface of a semiconductor substrate having at least one pn junction, and etching the portion not covered with the masking agent to form a mesa groove. A semiconductor device is manufactured by forming a pn junction on the inner surface of a mesa groove, coating the exposed pn junction with a passivation material such as glass, polyimide, or junction coating resin (JCR), and then depositing a metal electrode film on the substrate surface. Regarding the manufacturing method.

〔従来の技術〕[Conventional technology]

半導体素子を製造する際、半導体基板の一面から内面に
pn接合を露出させるメサ溝をウェットエツチングによ
り形成し、pn接合露出面をパッシベーション材料で被
覆し、さらに基板面に金属電極膜を被着するのは、信鯨
性の高い素子を量産するのに適した方法として知られて
いる。このような製造方法として、従来は、例えばpn
接合を形成したシリコン基板面を被覆しているS10よ
膜上に、マスク剤としてフォトレジスト、ポリイミドな
どを塗布し、フォトエツチングで任意のパターンのマス
クを形成したのちウェットエツチングを行い、エツチン
グ終了後マスク剤を除去し、露出したpn接合部にガラ
ス、ポリイミド、接合被覆樹脂などのバッシベーシッン
材をコーティングしていた、また、別の方法として、ウ
ェットエツチング前に全面サンドブラストを行い、シリ
コン基板表面の310.膜を除去し荒れた状態にした後
、マスク剤としてフォトレジスト、ポリイミドなどを用
い、バターニングを施してウェットエツチングを行い、
エツチング終了後、マスク剤を除去、またはそのままに
しておいて、露出したpn接合部にガラス、ポリイミド
または接合被覆樹脂などをコーティングしていた。
When manufacturing semiconductor devices, a mesa groove is formed by wet etching to expose a pn junction from one surface of a semiconductor substrate to the inner surface, the exposed surface of the pn junction is covered with a passivation material, and a metal electrode film is further coated on the substrate surface. This is known as a method suitable for mass-producing elements with high reliability. Conventionally, as such a manufacturing method, for example, pn
A photoresist, polyimide, etc. is applied as a masking agent onto the S10 film covering the surface of the silicon substrate on which the bond is formed, and a mask with an arbitrary pattern is formed by photoetching, and then wet etching is performed, and after the etching is completed. The masking agent was removed and the exposed pn junction was coated with a bashing material such as glass, polyimide, or bonding coating resin. Another method is to perform sandblasting on the entire surface before wet etching to remove the 310% of the silicon substrate surface. .. After removing the film and leaving it in a rough state, we perform buttering and wet etching using photoresist, polyimide, etc. as a masking agent.
After etching, the masking agent is removed or left as is, and the exposed pn junction is coated with glass, polyimide, bonding coating resin, or the like.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の製造方法において、ウェットエツチング前にサン
ドブラストを全く行わなかった場合、マスク剤と半導体
基板との密着性が弱く、最悪の場合、メサ溝のウェット
エツチング前にマスク剤の剥離などが生じ、また、露出
したpn接合をコーティングする際もバンシベーシッン
材料の密着性が悪く、問題となっていた。一方、ウェッ
トエツチング前にサンドブラストを行った面に対しては
、マスク剤の密着性は良いが蒸着膜の密着性が劣るので
、電極付けの時に蒸着による安定した電極膜の形成が不
可能となり、金属被膜を半導体基板上に付着させるため
に無電解めっきを用いなければならない、しかし、その
場合めっき液がガラス。
In conventional manufacturing methods, if sandblasting is not performed at all before wet etching, the adhesion between the masking agent and the semiconductor substrate is weak, and in the worst case, the masking agent may peel off before wet etching of the mesa groove. Also, when coating the exposed pn junction, the adhesion of the bancibasin material was poor, which was a problem. On the other hand, on the surface sandblasted before wet etching, the adhesion of the mask agent is good, but the adhesion of the vapor deposited film is poor, making it impossible to form a stable electrode film by vapor deposition when attaching the electrodes. Electroless plating must be used to deposit metal films onto semiconductor substrates, but in that case the plating solution is glass.

ポリイミド、JCRなどのパンシベーシッン材料膜に対
して悪影響を及ぼし特性の不安定をもたらす問題があっ
た。
There has been a problem in that it has an adverse effect on films made of pansibasin materials such as polyimide and JCR, resulting in unstable properties.

本発明の目的は、上記の問題を解決し、メサ溝形成のウ
ェットエツチング時のマスクの基板との密着性、バンシ
ベーシッン材とpn接合露出部との密着性および金属電
極と基板表面の密着性の良好な半導体素子の製造方法を
提供することにある。
An object of the present invention is to solve the above-mentioned problems and to improve the adhesion of the mask to the substrate during wet etching for forming mesa grooves, the adhesion between the bancibasin material and the exposed pn junction, and the adhesion between the metal electrode and the substrate surface. An object of the present invention is to provide a method for manufacturing a good semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために、本発明は、少なくとも一
つのpn接合を有する半導体基板の一面にマスク剤を被
着し、マスク剤で覆われない部分をエツチングすること
によりメサ溝を形成してメサ溝内面にpn接合を露出さ
せ、マスク剤を除去後露出したpn接合をパフシベーシ
ッン材料で被覆し、さらに半導体基板の少なくとも前記
一面に金属電極膜を被着することを含む半導体素子の製
造方法において、マスク剤を被着する前に半導体基板の
前記一面上に存在する酸化膜のメサ溝形成領域を含むそ
れよりやや広い領域を除去したのち、露出した半導体基
板面をサンドブラストで荒らすものとする。
In order to achieve the above object, the present invention applies a masking agent to one surface of a semiconductor substrate having at least one pn junction, and forms a mesa groove by etching the portion not covered with the masking agent. A method for manufacturing a semiconductor device, comprising: exposing a pn junction on an inner surface of a mesa groove; coating the exposed pn junction with a puffy basis material after removing a masking agent; and further depositing a metal electrode film on at least one surface of a semiconductor substrate. , before applying the masking agent, a slightly wider area of the oxide film on the one surface of the semiconductor substrate including the mesa groove formation region is removed, and then the exposed semiconductor substrate surface is roughened by sandblasting.

〔作用〕[Effect]

半導体基板面のメサ溝形成領域よりやや広い領域をサン
ドブラストし、その領域に存在した酸化膜を除去し、粗
面とすることによりメサ溝形成領域を除いて被着するマ
スク剤は、縁部が粗面上に接着するので、マスク剤の基
板面に対する密着性が向上する。エツチングによりメサ
溝形成後、マスク剤を除去し、露出pn接合をパフシベ
ーシッン材料で被覆する際も、パフシベーシッン材料膜
の縁部が基板の粗面上に接着するので、パフシベーシ四
ン材料と基板との密着性も向上する。しかも、メサ溝の
近傍以外の基板面は粗面化されていないので蒸着により
安定した電極膜の形成が可能になる。
By sandblasting an area slightly wider than the mesa groove formation area on the semiconductor substrate surface, removing the oxide film existing in that area and making the surface rough, the masking agent deposited on the semiconductor substrate except for the mesa groove formation area has a rough edge. Since it adheres to the rough surface, the adhesion of the masking agent to the substrate surface is improved. After forming a mesa groove by etching, when the masking agent is removed and the exposed pn junction is covered with a puffy basis material, the edge of the puffy basis material film adheres to the rough surface of the substrate, so the contact between the puffy basis material and the substrate is Adhesion is also improved. Moreover, since the substrate surface other than the vicinity of the mesa groove is not roughened, it is possible to form a stable electrode film by vapor deposition.

〔実施例〕〔Example〕

以下第1図ないし第4図を引用して本発明の一実施例に
ついて説明する。第1図(5)、 (bl、 telは
、シリコン基板の表面粗面化工程を示し、(8)は平面
図、(b)は断面図、(C)は(b)のA部拡大図であ
る0表面に平行なpn接合を形成したシリコン基板の表
面を被覆する5tozll* 2の一部分3を選択エツ
チングで除去した。除去した部分3は、後工程でメサ溝
を形成する領域を中心としてメサ溝の幅の缶板上の幅を
持った領域である。そしてこのS10.膜2を除去した
領域3をサンドブラストによって粗面化した。第2図(
al、 (b)、 (c)は、メサ溝のエツチング工程
を示し、第1図と同様(a)は平面図、(b)は断面図
、(C)は(blOA部拡大図である。この工程ではメ
サ溝4の形成領域以外をマスク剤としてのレジスト膜5
で被覆し、ウェットエツチングを行う。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. Figure 1 (5), (bl, tel) shows the surface roughening process of the silicon substrate, (8) is a plan view, (b) is a cross-sectional view, (C) is an enlarged view of part A of (b). A part 3 of 5tozll*2 covering the surface of the silicon substrate on which a pn junction parallel to the 0 surface was formed was removed by selective etching. This is a region on the can plate with a width equal to the width of the mesa groove. Then, this S10. Region 3 from which the film 2 was removed was roughened by sandblasting.
al, (b), and (c) show the etching process of the mesa groove, and similarly to FIG. 1, (a) is a plan view, (b) is a sectional view, and (C) is an enlarged view of the (blOA part). In this step, a resist film 5 is used as a masking agent in areas other than the area where the mesa groove 4 is formed.
and wet etching.

レジスト膜5は縁部がシリコン基板1表面のサンドブラ
ストされた領域3の上に被着するので、この領域で基板
に密着し、基板から@離することがない、ウェットエツ
チングの結果、メサ溝4が形成され、その内面にpn接
合が露出する。第3図では、このpn接合露出面にパン
シベーシッン材料としての接合被覆樹脂6をコーティン
グする。
Since the edge of the resist film 5 is deposited on the sandblasted area 3 on the surface of the silicon substrate 1, it adheres closely to the substrate in this area and does not separate from the substrate.As a result of wet etching, the mesa groove 4 is formed. is formed, and a pn junction is exposed on its inner surface. In FIG. 3, the exposed surface of the pn junction is coated with a bonding coating resin 6 as a pansibasin material.

この接合被覆樹脂6の縁部もサンドブラストされた領域
3に密着するので、メサ溝4の内面から剥離することが
ない、第4図は電極付は工程を示し、第4図fatでは
、必要によれば接合被覆樹脂6をマスクしてエツチング
により表面のsho、膜2を除去し、そのあとの第4図
(blでシリコン基板1の露出面に金属膜7を蒸着する
。基板面は平滑で蒸着膜は密着し、安定した電極膜7が
得られる。
Since the edge of this bonding coating resin 6 also adheres to the sandblasted area 3, it will not peel off from the inner surface of the mesa groove 4. According to the method, the bonding coating resin 6 is masked and the film 2 on the surface is removed by etching, and then the metal film 7 is deposited on the exposed surface of the silicon substrate 1 as shown in FIG. The deposited film adheres closely, and a stable electrode film 7 is obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、メサ溝形成領域に接する半導体基板表
面領域をサンドブラストで粗面化することにより、メサ
溝形成領域以外に被着されるマスク剤、メサ溝内面に被
覆されるパンシベーシ町ン材料が縁部でその粗面化領域
に密着して剥離することがなくなり、また粗面化されな
い領域には安定した電極付けが行えるので、信幀性の高
い半導体素子を製造することができる。
According to the present invention, by roughening the surface area of the semiconductor substrate in contact with the mesa groove forming area by sandblasting, a masking agent is applied to areas other than the mesa groove forming area, and a pansive material is coated on the inner surface of the mesa groove. The edges adhere to the roughened area and will not peel off, and electrodes can be stably attached to the non-roughened areas, making it possible to manufacture highly reliable semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al、 Cbl、 fclは本発明の一実施例
の粗面化工程を示し、fatは平面図、(b)は断面図
、(C)は(blのA部拡大図、第2図(al、 (b
l、 (C1は本発明の一実施例のメサ溝形成工程を示
し、(4)は平面図、(b)は断面図、(C)は(bl
OA部拡大図、第3図は本発明の一実施例のパフシベー
シッン工程を示す断面図、第4図+a+、(′blは本
発明の一実施例の電極付は工程を順次示す断面図である
。 1:シリコン基板、2 : Sin、膜、3:サンドブ
ラスト実施領域、4:メサ溝、5;レジスト膜、6:接
合被覆樹脂、7:金属電橋膜、    −7代理人4t
Jχ土 山 口  巌
Figure 1 (al, Cbl, fcl shows the roughening process of one embodiment of the present invention, fat is a plan view, (b) is a sectional view, (C) is an enlarged view of part A of (bl, second Figures (al, (b)
l, (C1 shows the mesa groove forming step of one embodiment of the present invention, (4) is a plan view, (b) is a cross-sectional view, (C) is (bl
An enlarged view of the OA part, FIG. 3 is a cross-sectional view showing the puff sealing process of an embodiment of the present invention, and FIG. 1: Silicon substrate, 2: Sin, film, 3: Sandblasting area, 4: Mesa groove, 5: Resist film, 6: Bonding coating resin, 7: Metal bridge film, -7 proxy 4t
Jχ soil Iwao Yamaguchi

Claims (1)

【特許請求の範囲】[Claims] 1)少なくとも一つのpn接合を有する半導体基板の一
面にマスク剤を被着し、マスク剤で覆われない部分をエ
ッチングすることによりメサ溝を形成してメサ溝内面に
pn接合を露出させ、マスク剤を除去後露出したpn接
合をパッシベーション材料で被覆し、さらに半導体基板
の少なくとも前記一面に金属電極膜を被着することを含
む半導体素子の製造方法において、マスク剤を被着する
前に半導体基板の前記一面上に存在する酸化膜のメサ溝
形成領域を含むそれよりやや広い領域を除去したのち、
露出した半導体基板面をサンドブラストで荒らすことを
特徴とする半導体素子の製造方法。
1) Apply a masking agent to one surface of a semiconductor substrate having at least one pn junction, and form a mesa groove by etching the portion not covered with the masking agent to expose the pn junction on the inner surface of the mesa groove, and then apply the mask. In a method for manufacturing a semiconductor device, the method includes covering the exposed pn junction with a passivation material after removing the masking agent, and further depositing a metal electrode film on at least one surface of the semiconductor substrate. After removing a slightly wider area including the mesa groove formation area of the oxide film existing on the one surface of the oxide film,
A method for manufacturing a semiconductor device, characterized by roughening the exposed surface of a semiconductor substrate by sandblasting.
JP8904489A 1989-04-07 1989-04-07 Manufacture of semiconductor element Pending JPH02267967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8904489A JPH02267967A (en) 1989-04-07 1989-04-07 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8904489A JPH02267967A (en) 1989-04-07 1989-04-07 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPH02267967A true JPH02267967A (en) 1990-11-01

Family

ID=13959892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8904489A Pending JPH02267967A (en) 1989-04-07 1989-04-07 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPH02267967A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137353B2 (en) 2002-09-30 2006-11-21 Tokyo Electron Limited Method and apparatus for an improved deposition shield in a plasma processing system
US7147749B2 (en) 2002-09-30 2006-12-12 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate with deposition shield in a plasma processing system
US7163585B2 (en) 2002-09-30 2007-01-16 Tokyo Electron Limited Method and apparatus for an improved optical window deposition shield in a plasma processing system
US7166166B2 (en) 2002-09-30 2007-01-23 Tokyo Electron Limited Method and apparatus for an improved baffle plate in a plasma processing system
US7166200B2 (en) 2002-09-30 2007-01-23 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate in a plasma processing system
US7204912B2 (en) 2002-09-30 2007-04-17 Tokyo Electron Limited Method and apparatus for an improved bellows shield in a plasma processing system
US7282112B2 (en) 2002-09-30 2007-10-16 Tokyo Electron Limited Method and apparatus for an improved baffle plate in a plasma processing system
US7291566B2 (en) 2003-03-31 2007-11-06 Tokyo Electron Limited Barrier layer for a processing element and a method of forming the same
US7552521B2 (en) 2004-12-08 2009-06-30 Tokyo Electron Limited Method and apparatus for improved baffle plate
US7560376B2 (en) 2003-03-31 2009-07-14 Tokyo Electron Limited Method for adjoining adjacent coatings on a processing element
US7601242B2 (en) 2005-01-11 2009-10-13 Tokyo Electron Limited Plasma processing system and baffle assembly for use in plasma processing system
US8877002B2 (en) 2002-11-28 2014-11-04 Tokyo Electron Limited Internal member of a plasma processing vessel

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7282112B2 (en) 2002-09-30 2007-10-16 Tokyo Electron Limited Method and apparatus for an improved baffle plate in a plasma processing system
US7566368B2 (en) 2002-09-30 2009-07-28 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate in a plasma processing system
US7163585B2 (en) 2002-09-30 2007-01-16 Tokyo Electron Limited Method and apparatus for an improved optical window deposition shield in a plasma processing system
US7166166B2 (en) 2002-09-30 2007-01-23 Tokyo Electron Limited Method and apparatus for an improved baffle plate in a plasma processing system
US7166200B2 (en) 2002-09-30 2007-01-23 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate in a plasma processing system
US7204912B2 (en) 2002-09-30 2007-04-17 Tokyo Electron Limited Method and apparatus for an improved bellows shield in a plasma processing system
US7566379B2 (en) 2002-09-30 2009-07-28 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate with deposition shield in a plasma processing system
US7137353B2 (en) 2002-09-30 2006-11-21 Tokyo Electron Limited Method and apparatus for an improved deposition shield in a plasma processing system
US7147749B2 (en) 2002-09-30 2006-12-12 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate with deposition shield in a plasma processing system
US8877002B2 (en) 2002-11-28 2014-11-04 Tokyo Electron Limited Internal member of a plasma processing vessel
US7560376B2 (en) 2003-03-31 2009-07-14 Tokyo Electron Limited Method for adjoining adjacent coatings on a processing element
US7291566B2 (en) 2003-03-31 2007-11-06 Tokyo Electron Limited Barrier layer for a processing element and a method of forming the same
US7552521B2 (en) 2004-12-08 2009-06-30 Tokyo Electron Limited Method and apparatus for improved baffle plate
US7601242B2 (en) 2005-01-11 2009-10-13 Tokyo Electron Limited Plasma processing system and baffle assembly for use in plasma processing system

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