JPH02267997A - Mounting structure for amplifier circuit - Google Patents

Mounting structure for amplifier circuit

Info

Publication number
JPH02267997A
JPH02267997A JP1088697A JP8869789A JPH02267997A JP H02267997 A JPH02267997 A JP H02267997A JP 1088697 A JP1088697 A JP 1088697A JP 8869789 A JP8869789 A JP 8869789A JP H02267997 A JPH02267997 A JP H02267997A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
inverting input
amplifier circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1088697A
Other languages
Japanese (ja)
Other versions
JP2588606B2 (en
Inventor
Satoru Ishii
哲 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1088697A priority Critical patent/JP2588606B2/en
Publication of JPH02267997A publication Critical patent/JPH02267997A/en
Application granted granted Critical
Publication of JP2588606B2 publication Critical patent/JP2588606B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To suppress the effect of flux that is cut by a circuit on the inverting input side and one on the non-inverting input side, i.e., that of electromagnetic induction to a small extent by disposing the circuits on the inverting input side and that of non-inverting input side substantially in symmetry on the surface and rear of a printed wiring board. CONSTITUTION:Resistances 4 and 5 at the surface of a printed wiring board 14 and the resistances 6 and 7 at the rear of the above board are disposed in symmetry and similarly FETs 8 and 9 are disposed in symmetry at the surface and rear of the board 14. As input circuits at non-inverting and inverting sides are disposed substantially in symmetry at both the surface and rear of the printed wiring board, a loop that is subjected to electromagnetic induction is minimized to a certain extent that is caused only by the thickness of the above printed wiring board.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、プリント配線板に実装される増幅回路の実装
構造に関するもので、とくに、電磁的なフラックスの影
響を最小限に抑えるようにした実装構造に関するもので
ある。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mounting structure of an amplifier circuit mounted on a printed wiring board, and in particular, it relates to a mounting structure of an amplifier circuit mounted on a printed wiring board, and in particular, a mounting structure that minimizes the influence of electromagnetic flux. It is related to the mounting structure.

[従来の技術] 一般に、差動増幅回路は、第2図のような回路構成にな
っている。
[Prior Art] Generally, a differential amplifier circuit has a circuit configuration as shown in FIG.

第2図において、1は非反転入力端子、2は反転入力端
子、3は接地端子(GND)、45.6.7は抵抗、8
.9はFET、10は内部の増幅回路の一部分、11は
定電流回路、13は出力端子である。
In Figure 2, 1 is a non-inverting input terminal, 2 is an inverting input terminal, 3 is a ground terminal (GND), 45.6.7 is a resistor, 8
.. 9 is an FET, 10 is a part of an internal amplifier circuit, 11 is a constant current circuit, and 13 is an output terminal.

この回路において、人力信号が平衡の場合には前記端子
1.2の間に入力されるが、不平衡の場合は前記端子1
または2のいずれかが接地される。ここでは、不平衡の
場合を例にとって説明することにし、前記端子2を接地
するとともに、この場合の該端子1を、信号入力端子1
2と呼ぶことにする。
In this circuit, when the human input signal is balanced, it is input between the terminals 1 and 2, but when it is unbalanced, it is input between the terminals 1 and 2.
or 2 is grounded. Here, an unbalanced case will be explained as an example, and the terminal 2 is grounded, and the terminal 1 in this case is connected to the signal input terminal 1.
I'll call it 2.

この回路をプリント配線板14に実装すると、たとえば
、第3図に示すように構成される。
When this circuit is mounted on the printed wiring board 14, it will be configured as shown in FIG. 3, for example.

また上記のような負帰還増幅回路のブロック図は、一般
に、第4図のように表わされる。
Further, a block diagram of the above-mentioned negative feedback amplifier circuit is generally represented as shown in FIG.

第4図において、15は入力回路部における伝達関数で
あり、上記の例では、抵抗4および抵抗5による分圧比
に相当する。16は減算器であり、FET8およびFE
T9による差動部分に相当し、非反転入力と反転入力と
の差成分を取り出す機能だけを抽出している。17は増
幅回路全体のオーブンループの伝達関数であり、非反転
入力と反転入力との差が増幅され、出力端子13に伝達
される増幅度に相当する。
In FIG. 4, reference numeral 15 represents a transfer function in the input circuit section, which corresponds to the voltage division ratio of resistors 4 and 5 in the above example. 16 is a subtracter, FET8 and FE
This corresponds to the differential part by T9, and extracts only the function of extracting the difference component between the non-inverting input and the inverting input. 17 is a transfer function of the oven loop of the entire amplifier circuit, and corresponds to the degree of amplification at which the difference between the non-inverting input and the inverting input is amplified and transmitted to the output terminal 13.

18は負帰還ネットワークにおける伝達関数であり、抵
抗7および抵抗6による分圧比に相当する。
18 is a transfer function in the negative feedback network, and corresponds to the voltage division ratio by the resistors 7 and 6.

[発明が解決しようとする課題] 前述した第4図のような負帰還増幅回路において、信号
入力端子12から出力端子13へひずみなく忠実に信号
を伝達するためには、入力回路部における伝達関数15
および負帰還ネットワークにおける伝達関数18が、完
全にリニアでなければならない、増幅回路のオープンル
ープの伝達量@、+7における非線形性や電1+f1誘
導などの外乱は負帰還によって改善されるが、入力回路
部における伝達関数15および負帰還ネットワークにお
ける伝達関数18に関しては、非線形性があったり、電
磁誘導などの外乱があったりすると、もはや、負帰還に
よフて改善されることは望めない。
[Problems to be Solved by the Invention] In the negative feedback amplifier circuit as shown in FIG. 15
And the transfer function 18 in the negative feedback network must be completely linear. Disturbances such as nonlinearity in the open loop transfer @, +7 of the amplifier circuit and electric 1 + f1 induction can be improved by negative feedback, but the input circuit Regarding the transfer function 15 in the section and the transfer function 18 in the negative feedback network, if there is nonlinearity or disturbance such as electromagnetic induction, it can no longer be expected to be improved by negative feedback.

第2図の回路に戻って考えると、抵抗4〜7の線形性お
よび図示したループしに誘導されるフラックスの影響が
問題となる。抵抗の線形性は、定格に対して余裕を持っ
た使い方をしておれば、問題になることはまずないので
、通常は、電磁誘導の影響が問題になることが多い。
Returning to the circuit of FIG. 2, the linearity of resistors 4-7 and the effect of the flux induced in the illustrated loop become an issue. The linearity of a resistor is rarely a problem as long as it is used with plenty of room for its rating, so the effects of electromagnetic induction are usually a problem.

増幅器を有する機器において、次のような例を上げるこ
とができる。
The following examples can be given for devices with amplifiers.

すなわち、第1に、電源トランスからのフラックスを受
け、増幅出力に電源周波数およびその高周波が現われて
しまう。第2に、コンデンサへのチャージ・ディスチャ
ジを盛んに行なう回路(たとえば、電源回路、スイッチ
ング電源など)からのフラックスが飛び付く。第3に、
他の機器からのパルス状の雑音が、増幅出力に現われる
。第4に、B級増幅器では、正側の半サイクルと負側の
半サイクルとで出力段の電流ルートが常に変化するので
、誘導されるフラックスの影響が正負アンバランスだと
偶数次のひずみとして出力に現われる。
That is, first, the power supply frequency and its high frequency appear in the amplified output due to the flux from the power transformer. Second, flux from circuits that actively charge and discharge capacitors (for example, power supply circuits, switching power supplies, etc.) jumps to them. Thirdly,
Pulsed noise from other equipment appears on the amplified output. Fourth, in a class B amplifier, the current route in the output stage always changes between the positive half cycle and the negative half cycle, so if the influence of the induced flux is unbalanced, it will be treated as even-order distortion. Appears in the output.

以上述べたように、非反転側の入力回路と反転側の入力
回路との間に、実装上、少しでも、面積が存在すると、
原理的に上記のような電磁誘導が生じてしまうという問
題点がある。
As mentioned above, if there is even a small area between the non-inverting side input circuit and the inverting side input circuit,
There is a problem in that electromagnetic induction as described above occurs in principle.

本発明は、このような問題点を解決しようとするもので
ある。すなわち、本発明は、電磁誘導の影響を極少に抑
えることができる増幅回路の実装構造を提供することを
目的とするものである。
The present invention attempts to solve these problems. That is, an object of the present invention is to provide a mounting structure for an amplifier circuit that can minimize the influence of electromagnetic induction.

[課題を解決するための手段コ 上記目的を達成するために、本発明は、プリント配線板
に実装された差動増幅回路において、反転入力側の回路
と非反転入力側の回路とが、前記プリント配線板の両面
に実質的に対称に配置されているようにした。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a differential amplifier circuit mounted on a printed wiring board, in which an inverting input side circuit and a non-inverting input side circuit are connected to the They are arranged substantially symmetrically on both sides of the printed wiring board.

[作   用] 本発明によれば、非反転側の入力回路と反転側の入力回
路とを、プリント配線板の両面に実質的に対称に配置し
ているので、1に磁誘導を受けるループは、プリント配
線板の厚みで生じる程度の非常に小さいものとなる。
[Function] According to the present invention, since the input circuit on the non-inverting side and the input circuit on the inverting side are arranged substantially symmetrically on both sides of the printed wiring board, the loop receiving magnetic induction in 1 is , it becomes a very small one that occurs due to the thickness of the printed wiring board.

[実 施 例] 第1図(a) 、 (b)は本発明の一実施例を示した
斜視図である。
[Embodiment] FIGS. 1(a) and 1(b) are perspective views showing an embodiment of the present invention.

そして、第1図における符号は、第3図の符号と対応す
る。すなわち、この実施例では、フリント配線板14の
両面に部品や配線パターンを対称に配置するという前提
で表面実装を基本にしている。たとえば、プリント配線
板14の表面の抵抗4,5に対し、裏面の抵抗6.7が
それに対称に、また表面のFET8に対し、裏面のFE
T9がそれに対称に配置されている。
The symbols in FIG. 1 correspond to the symbols in FIG. 3. That is, this embodiment is based on surface mounting on the premise that components and wiring patterns are arranged symmetrically on both sides of the flint wiring board 14. For example, the resistance 6.7 on the back side is symmetrical to the resistance 4, 5 on the front side of the printed wiring board 14, and the FE on the back side is symmetrical to the resistance 6.7 on the front side.
T9 is arranged symmetrically thereto.

なお第1図では、両面の部品配置などがわかりやすいよ
うに、前記プリント配線板14の厚みを誇張して示して
いるが、実際は、第3図のように薄いものである。
Although the thickness of the printed wiring board 14 is exaggerated in FIG. 1 to make it easier to understand the arrangement of components on both sides, it is actually thin as shown in FIG. 3.

このように、プリント配線板14の両面に部品や配線パ
ターンを対称に配置することにょって、第1図(N  
にみられる?!磁誘導を受けるループしは、プリント配
線板14の厚みで生じる程度の非常に小さいものとなる
In this way, by symmetrically arranging components and wiring patterns on both sides of the printed wiring board 14, the parts and wiring patterns shown in FIG.
Can you see it? ! The loops subjected to magnetic induction are extremely small and occur due to the thickness of the printed wiring board 14.

なお上記実施例では、ミクロ的にみると、プリント配線
板14の裏面側(下面側)で、信号入力端子12を避け
るために、配線パターンを少しよけており、完全には両
面が対称に配置されていないが、この程度のことは、実
質的に対称ということができる。もちろん、端子にも表
面実装タイプのものを用いれば、完全に対称にすること
が可能である。また上記実施例では、差動増幅としてF
ET(ディスクリートタイプ)を用いているが、トラン
ジスタや、これらが集積化された演算増幅ICなどであ
ってもよい。さらに、説明は不平衡差動増幅回路を用い
て行なったが、平衡増幅回路でも、同様に実施すること
ができる。
In the above embodiment, from a microscopic perspective, the wiring pattern is slightly shifted on the back side (lower side) of the printed wiring board 14 in order to avoid the signal input terminal 12, so that both sides are not completely symmetrical. Although they are not arranged, to this extent it can be said that they are substantially symmetrical. Of course, if surface mount type terminals are used, it is possible to make the terminals completely symmetrical. Further, in the above embodiment, F is used as a differential amplification.
Although ET (discrete type) is used, transistors or operational amplifier ICs in which these are integrated may also be used. Further, although the description has been made using an unbalanced differential amplifier circuit, the present invention can be similarly implemented using a balanced amplifier circuit.

[発明の効果コ 以上説明したように、本発明によれば、反転入力側の回
路と非反転入力側の回路とを、プリント配線板の両面に
実質的に対称に配置したので、そこを切るフラックスの
影響、つまり、電磁銹導の影響を、極小に抑えることが
できる。
[Effects of the Invention] As explained above, according to the present invention, the circuit on the inverting input side and the circuit on the non-inverting input side are arranged substantially symmetrically on both sides of the printed wiring board. The influence of flux, that is, the influence of electromagnetic corrosion, can be minimized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) 、 (b)は本発明の一実施例を示した
斜視図、第2図は従来の増幅回路の一例を示した説明図
、第3図は同じく増幅回路の実装の一例を示した斜視図
、第4図は同じく増幅回路をブロック図で示した説明図
である。 1・・・非反転入力端子 2・・・反転入力端子3・・
・接地端子    4,5,6.7・・・抵抗8.9・
・・FET    12・・・信号入力端子13・・・
出力端子   14・・・プリント配線板。 他4名 第1図 第2図 第4図
Figures 1 (a) and (b) are perspective views showing one embodiment of the present invention, Figure 2 is an explanatory diagram showing an example of a conventional amplifier circuit, and Figure 3 is an example of mounting the amplifier circuit. FIG. 4 is an explanatory diagram similarly showing the amplifier circuit in a block diagram. 1...Non-inverting input terminal 2...Inverting input terminal 3...
・Ground terminal 4, 5, 6.7...Resistance 8.9・
...FET 12...Signal input terminal 13...
Output terminal 14...Printed wiring board. 4 others Figure 1 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1 プリント配線板に実装された差動増幅回路において
、反転入力側の回路と非反転入力側の回路とが、前記プ
リント配線板の両面に実質的に対称に配置されているこ
とを特徴とする増幅回路の実装構造。
1. A differential amplifier circuit mounted on a printed wiring board, characterized in that an inverting input side circuit and a non-inverting input side circuit are arranged substantially symmetrically on both sides of the printed wiring board. Mounting structure of amplifier circuit.
JP1088697A 1989-04-07 1989-04-07 Mounting structure of amplifier circuit Expired - Fee Related JP2588606B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1088697A JP2588606B2 (en) 1989-04-07 1989-04-07 Mounting structure of amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1088697A JP2588606B2 (en) 1989-04-07 1989-04-07 Mounting structure of amplifier circuit

Publications (2)

Publication Number Publication Date
JPH02267997A true JPH02267997A (en) 1990-11-01
JP2588606B2 JP2588606B2 (en) 1997-03-05

Family

ID=13950051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1088697A Expired - Fee Related JP2588606B2 (en) 1989-04-07 1989-04-07 Mounting structure of amplifier circuit

Country Status (1)

Country Link
JP (1) JP2588606B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5899863U (en) * 1981-12-26 1983-07-07 富士電機株式会社 hybrid integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5899863U (en) * 1981-12-26 1983-07-07 富士電機株式会社 hybrid integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906411B1 (en) 2000-06-29 2005-06-14 Mitsubishi Denki Kabushiki Kaisha Multilayer substrate module and portable wireless terminal

Also Published As

Publication number Publication date
JP2588606B2 (en) 1997-03-05

Similar Documents

Publication Publication Date Title
US6556077B2 (en) Instrumentation amplifier with improved AC common mode rejection performance
JPH02267997A (en) Mounting structure for amplifier circuit
Nako et al. A note on the bandwidth of negative group delay filters
Lee Low-voltage op amp design and differential difference amplifier design using linear transconductor with resistor input
JPH0346581Y2 (en)
JP2002091577A (en) Electronic load device
US5650748A (en) Ultra-stable gain circuit
Bhaskar et al. Single operational transresistance amplifier‐based grounded resistance‐controlled synthetic inductor configuration
US4074215A (en) Stable gyrator network for simularity inductance
US7054439B2 (en) Differential input stage for electronic equipment, comprising means for reducing interference caused by a voltage or current in common mode
KR810001083B1 (en) Audio-frequency power amplifier
CA1063193A (en) Single amplifier network for simulating a super-inductor circuit
EP1392195B1 (en) Integrated low-corner frequency high pass filter circuit
US11689166B2 (en) Circuitry for reducing distortion over a wide frequency range
Woo Digitally programmable gain amplifiers with arbitary range of integer values
RU2115224C1 (en) Audio-frequency power amplifier
JPS61200761A (en) System for detecting and supressing induced broadcast wave
KR200315301Y1 (en) Open loop type current sensor including compensation sercuit
JPH01213008A (en) Amplification circuit
JPS5918368Y2 (en) Current detection circuits such as power amplifier circuits
JPS63314009A (en) Differental amplifier circuit
JPH03117012A (en) Amplifier circuit
JPH0418247Y2 (en)
JPH0495406A (en) Differential amplifier circuit
KR960001117B1 (en) Sine wave ring generation circuit

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081205

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees