JPH0226802B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an amplifier having a plurality of feedback circuits in advance, in which a control signal is applied to the feedback circuits to independently conduct or cut off the feedback circuits, thereby adjusting the feedback constant. This relates to the selection of variable gain amplifiers.

FIG. 1 shows a conventional variable gain amplifier of this type. In FIG. 1, a resistor 10 is connected between an inverting input terminal 5 and an output terminal 6 of an operational amplifier 3, to which two positive and negative power supplies (+B, -B) are supplied to power supply terminals 1 and 2, respectively. . Inverting input terminal 5
is a resistor 11, a transistor 13, an emitter and a collector of this transistor 13,
The emitters are connected to a reference potential point (ground point) 9 via a switch circuit 17 consisting of transistors 14 of the same conductivity type, respectively connected. The bases of transistor 13 and transistor 14 are connected to control terminal 7. The inverting input terminal 5 is further connected to the reference potential point 9 via a resistor 12 and a switch circuit 18 consisting of a transistor 15 and a transistor 16 of the same conductivity type in which the emitter, collector, and emitter of the transistor 15 are connected, respectively. be done. The bases of transistor 15 and transistor 16 are connected to control terminal 8.

The circuit shown in FIG. 1 inputs the non-inverting input terminal 4 and the output terminal 6 of an operational amplifier 3, which can select the closed loop gain by applying a control signal to the control terminals 7 and 8, respectively. It operates as a variable gain amplifier with output.
That is, when the control terminal 7 and the control terminal 8 supply the base currents necessary for the transistors 13 and 14 and the transistors 15 and 16 to become conductive, respectively, the transistors 13, 14, 15, and 16 become conductive. However, when the base current is not supplied from the control terminal 7 and the control terminal 8, each transistor 13, 1
4, 15 and 16 are in the cut-off state. Therefore, the control terminal 7 and the transistors 13, 14
and control terminal 8 and transistors 15, 16
constitute a switch circuit 17 and a switch circuit 18 which independently conduct and open the closed loop circuit of the operational amplifier 3.

Let G _V be the closed loop gain due to the switch operations of the switch circuit 17 and the switch circuit 18 of the variable gain amplifier _shown in FIG. 3) given by Eq. When the switch circuit 17 is in a conductive state and the switch circuit 18 is in an open state, G _V = 1 + R ₁₀ /R ₁₁ ... (1) where, R ₁₀ : resistance value of resistor 10, R ₁₁ : resistance value of resistor 11
Resistance value of switch circuit 17 in open state, switch circuit 1
When switch circuit 8 is in conduction state, G _V = 1 + R ₁₀ /R ₁₂ ...(2) However, R ₁₂ : resistance value of resistor 12 When switch circuit 17 and switch circuit 18 are both in conduction state, G _V = 1 + R ₁₀ /R ₁₁ R ₁₂ ...(3) However, R ₁₁ R ₁₂ : Parallel combined resistance value of resistor 12 In this way, the gain can be varied by controlling the two switch circuits 17 and 18, but the conventional method shown in FIG. The circuit example has the disadvantage that the offset occurring in the output of the operational amplifier 3 is large. FIG. 2 shows the offset of the conventional circuit shown in FIG.

In FIG. 2, there is an input offset voltage 19 between the inverting input terminal 5 of the operational amplifier 3 and the differential input of the operational amplifier, and the switch circuits 17 and 1
8, transistors 13 and 14 constituting these
and offset voltage 20 and offset voltage 21 by transistors 15 and 16, respectively.
occurs. In FIG. 2, the offset voltages 19, 2
0 and 21 are equivalently shown as voltage sources,
Its polarity is arbitrary. In addition, the transistor 13
In 1 to 16, switches are indicated by a switch symbol.

In the amplifier 3 in which the offset voltages 19, 20, and 21 are shown as shown in FIG. 2, if the offset voltage generated at the output of the operational amplifier 3 when only the switch circuit 17 is conductive is V _OS6 , then V _OS6 is ( 4) Given by Eq.

V _OS6 = (1 + R ₁₀ / R ₁₁ ) × (V _OS19 + V _OS20 ) ...(4) However, V _OS19 : Voltage value of offset voltage 19 V _OS20 : Offset voltage value Also, when only the switch circuit 18 is in a conductive state If the output offset of is V _OS6 ', then V _OS6 ' is similarly given by equation (5).

V _OS6 ′=(1+R ₁₀ /R ₁₂ )×(V _OS19 +V _OS21 )……(5
) However, V _OS21 : Voltage value of offset voltage 21 From equations (4) and (5), the input conversion offset voltage in each case is V _OS19 + V _OS20 and
V _OS19 + V _OS21 . Here, offset voltage 2
0 and the offset voltage 21 are given by the collector-emitter potential difference V _{CE (sat)} when the transistors 13 and 14 and the transistors 15 and 16 which perform the switching operation are in the switching operation, that is, when these transistors are saturated. Yes, differential input offset voltage 1 of operational amplifier 3
The level is significantly higher than that of 9. In other words, the relationship shown in equation (6) is usually established.

V ₁₉ ≪V ₂₀ , V ₂₁ ...(6) In addition, the saturation voltage between the collector and emitter of each of the transistors 15 and 16 varies widely depending on the element, and when the gain is switched by the switch circuits 17 and 18, The offset generated in circuits 17 and 18 will vary significantly depending on the selection of the switch circuits. As a result, the input conversion offset voltage fluctuates each time, which is a disadvantage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain amplifier that has little input-referred offset fluctuation when switching the gain and can reduce its absolute value.

The amplifier according to the present invention includes a switch circuit for changing the gain, which has an inverting input width, a non-inverting input end, and an output end, the non-inverting input end being connected to a reference potential point, and the output of the output end being connected to a reference potential point. It is characterized by being constructed of a buffer circuit that is fully fed back to the inverting input terminal, and will be explained in detail below with reference to the drawings.

FIG. 3 shows an amplifier according to an embodiment of the present invention. In FIG. 3, differential input type buffer circuits 22 and 23 are connected to the reference potential point 9 at the other ends of a resistor 11 and a resistor 12, respectively, which are connected to the inverting input terminal 5 of the operational amplifier 3. ing.
Each input reference potential point 9 of buffer circuits 22 and 23 is connected, and each output is connected to resistors 11 and 12. Control terminals 7 and 8 are connected to buffer circuits 22 and 23, respectively,
By applying control signals to the control terminals 7 and 8, the buffer circuits 22 and 23 can be turned on and off to change the closed loop gain of the operational amplifier 3. That is, the closed loop gain _GV of the operational amplifier 3 is expressed by the above equation (1) when the buffer circuit 22 is on and the buffer circuit 23 is off, and when the buffer circuit 22 is off and the buffer circuit 23 is on, The above equation (2) is given by the above equation (2), and when the buffer circuits 22 and 23 are both in the on state, the above equation (3) is given.

The _input equivalent offset voltage in the amplifier shown in FIG. The offset voltage _VOS22 of each of the buffer circuits 22 and 23 constituting the
and V _OS23 , when only the buffer circuit 22 is on, V _OS3 + V _OS22 , only the buffer circuit 23
When in the ON state, it is given by V _OS3 + V _OS23 . Here, the offset voltages _VOS22 and _VOS23 of the buffer circuits 22 and 23 are given by the differential input offset voltage of the buffer circuits, so the switch circuit 17 in the conventional circuit example shown in FIG.
and 18 resulting in offset voltages V _OS20 and V _OS21
It can be made significantly smaller than that. That is, the relationship expressed by equation (7) holds true regarding the offset voltage generated in the gain switching circuit.

V _OS22 , V _OS23 ≪ V _OS20 , V _OS21 (7) Therefore, regarding the input equivalent offset voltage of the operational amplifier 3, the relationships of equations (8) and (9) hold similarly.

V _OS3 +V _OS22 , V _OS3 +V _OS23 << _{V OS19} +V _OS20 , V _OS19 +V _OS21 ...(8) V _OS3 V _OS19 ...(9) Also, since the buffer circuits 22 and 23 are of differential type, These buffer circuits 22, 2
It is possible to suppress the mutual difference in the offset voltage levels of the three offset voltage levels. In other words, the variation in the input equivalent offset when the gain of the amplifier 3 is changed can be made smaller than in the conventional case.

As described above, according to the present invention, the offset caused by the closed-loop gain switching means can be significantly reduced compared to the conventional method, and furthermore, the input-referred offset voltage level fluctuation at the time of each gain switching can be reduced. It becomes possible.

FIG. 4 shows the buffer circuits 22, 2 in FIG.
3 is a concrete circuit example of the present invention in which the circuit shown in FIG.
The buffer circuit 22 (23) has transistors 24, 25 (30, 31) that constitute a differential amplifier, and the base of one transistor 24 (30) serves as an input and is connected to the reference potential point 9. . The transistor 26 (32) is of a multi-collector type, with one collector connected to the base and serving as an active load for the differential amplifier of the transistors 24 and 25 (30, 31). The collector output of transistor 25 (31) is input to emitter follower type transistor 27 (33). transistor 27
The output of (33) is connected to resistor 11 (12) and to the base of transistor 25 (31), resulting in a full feedback configuration. Transistors 28 and 29 (34 and 35) constitute the current source of the differential amplifier and the current source load of transistor 27 (33), respectively, their bases connected to control terminal 7.
(8). Therefore, control terminal 7
When a high-level control signal is not input to (8), the transistors 28 and 29 (34, 35) are turned off, and the buffer circuit 22 (34) is also turned off.

As described above, regarding the present invention, in FIGS. 3 and 4, two-terminal circuits 37 and 38 connected between the inverting input terminal 5 of the operational amplifier 3 and the reference potential point 9 and the inverting input terminal 5 of the operational amplifier 3 are shown. and output terminal 6
5, the two-terminal circuit 37 is a series circuit of a resistor 41 and a capacitor 42, and the two-terminal circuit 36 is a resistor 39. Even if it is configured with a parallel circuit of the capacitor 40 and the like, there will be no problem, and other circuit configurations may be used. Furthermore, if the present invention is implemented using a semiconductor integrated circuit,
It is even more effective. Furthermore, it is clear that the same effect can be obtained even if the feedback circuit is realized by one circuit or by connecting three or more circuits to increase the gain switching.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is an equivalent circuit diagram of FIG. 1 regarding offset voltage. FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing a further embodiment of the embodiment of FIG. FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1, 2...Power supply terminal, 3...Operation amplifier,
4...Non-inverting input terminal, 5...Inverting input terminal, 6
... Output terminal, 7, 8 ... Control terminal, 9 ... Reference potential point, 10 to 12, 39, 41 ... Resistor, 13
~16,24~35...transistor, 17~1
8... Switch circuit, 19-21... Offset voltage, 22, 23... Buffer circuit, 36-3
8...2 terminal circuit, 40, 42...capacitor.

Claims (1)

[Claims] 1. A first two-terminal circuit with one end connected to the feedback terminal of the amplifier, a switch circuit connected between the other end of this circuit and a reference potential point, and a circuit between the feedback terminal and the output terminal of the amplifier. and a second two-terminal circuit connected between the buffer circuit and a second two-terminal circuit connected between the buffer circuit and a second two-terminal circuit connected between the buffer circuit and a second two-terminal circuit. and an output terminal are respectively connected to the reference potential point and the other terminal of the first two-terminal circuit, the output at the output terminal of the buffer circuit is fully fed back to the inverting input terminal, and the control terminal is connected to the second terminal of the first two-terminal circuit. When the level is 1, the buffer circuit is activated and sets the output terminal to the potential of the reference potential point,
A variable gain amplifier characterized in that when the control terminal is at a second level, the buffer circuit is inactive and the output terminal is in a high impedance state.