JPH0226818B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of driving an insulated gate type MOS transistor through a transformer winding for high speed operation.

MOS transistors have electrostatic capacitance (hereinafter abbreviated as gate capacitance) between the gate and source, and especially those for large currents have a gate capacitance of 1000 pF to 2000 pF. In order to drive a MOS transistor at high speed, a driving method that can charge and discharge the gate capacitance in a short time is required. In other words, the gate electrode (hereinafter simply referred to as gate) of the MOS transistor is driven with low impedance during the period when the MOS transistor is turned on or turned off. It is necessary to.

Hereinafter, this type of conventional driving method will be explained with reference to the drawings. Figure 1 shows a circuit using a conventional driving method, with 1 and 2 being input terminals, 3 being a transformer, and 4 and 5 being a transformer.
MOS transistors, 6, 7, 8 are output terminals, 9,
10 is a switch element, 11 is a DC power supply, and 12 is a resistor. The resistor 12, the first winding _n1 of the transformer 3, and the switch element 9 are connected in series with the DC power supply 11, and the resistor 12 and the transformer 3 are connected in series. The third winding n ₃ of the transformer 3 and the switch element ₁₀ are connected between the connection point of the first winding n 1 and the negative terminal of the DC power supply 11, and the input terminals 1 and 2 are connected to the switch elements 9 and 10. control electrodes, that is, switch elements 9 and 10 in FIG.
Since it uses a MOS transistor, it is connected to the gate. The first winding n ₁ and the third winding of transformer 3
In _n3 , the number of windings is the same, but the winding direction is opposite. The second winding n ₂ of the transformer 3 is connected between the gate and the source of the MOS transistor 4, and the fourth winding n ₄ of the transformer 3 is connected between the gate and the source of the MOS transistor 5, the MOS transistor The drain of MOS transistor 4 (indicated by D) is connected to output terminal 6, the drain of MOS transistor 5 is connected to output terminal 8, and each source (indicated by S) of MOS transistors 4 and 5 is connected to output terminal 7. The function of this circuit is to conduct the MOS transistors 4 and 5 alternately and without overlapping with the input signals applied to the input terminals 1 and 2.The operation will be explained below using the operating waveforms shown in Figure 2. do.

In Fig. 2, A is the signal waveform of input terminal 1, B
is the signal waveform of the input terminal 2, C is the gate-source voltage waveform of the MOS transistor 5, and D is the gate-source voltage waveform of the MOS transistor 4. At time _t1, as shown in waveform A, when input terminal 1 becomes low level, switch element 9 turns off,
Since input terminal 2 is at a high level as shown in waveform B, switch element 10 is in a conductive state. When the switch element 9 is cut off, a positive voltage is applied between the terminals of the third winding _n3 of the transformer 3 at the winding start end (indicated by a black circle) through the resistor 12, resulting in a MOS waveform as shown in waveform C. The gate-source voltage of transistor 5 becomes negative, and as shown in waveform D, the MOS
The gate-source voltage of transistor 4 becomes positive. Here, MOS transistors 4 and 5 are N-channel enhancement type transistors, and are shut off when the gate-source voltage is less than V _th .
Assuming that it is conductive at V _th or higher, the MOS transistor 4 becomes conductive at time t ₂ . At this time, the voltage between the gate and source of the MOS transistor 5 is in a cutoff state because a reverse voltage is applied. time t ₃
When the signal at input terminal 1 becomes high level, switch element 9 is turned on, and both switch elements 9 and 10 are in a conductive state for a period up to time _t4 . When both switch elements 9 and 10 become conductive at time t ₃ , the series circuit of the first winding n ₁ and the third winding n ₃ of the transformer 3 is in a short-circuited state, that is, the starting end of the first winding ( black circle mark)
and the winding end of the third winding become the same potential, and the charge that had charged the gate capacitance of the MOS transistor 4 before time _t3 becomes equivalent to shorting the second winding _n2 , and is transformed. Since the discharge occurs through the second winding _n2 of the device 3, the voltage between the gate and source of the MOS transistor 4 quickly becomes zero, and the MOS transistor 4 can be cut off quickly. At time _t4 , when the signal at input terminal 2 becomes low level as shown in waveform B, switch element 10 is turned off, and the gate-source voltage of MOS transistor 5 becomes a positive voltage as shown in waveform C at time _t5 . Gate-source voltage
When V _th is exceeded, the MOS transistor becomes conductive, and when the signal at input terminal 2 becomes high level at time t ₆ .
MOS transistor 5 is cut off and the state returns to the state before time _t1 .

As explained above, this circuit has input terminals 1 and 2.
By applying alternately low level signals to
MOS transistors 4 and 5 are alternately turned on. By the way, the drawback _{of this} circuit is _that the resistor ₁₂ is
and MOS transistor 4 through transformer 3
(or MOS transistor 5) because the gate capacitance of MOS transistor 4 (or MOS transistor 5) is being charged.
This is because the gate drive waveform of the MOS transistor 5) becomes dull. When the gate capacitance of the MOS transistor 4 is charged in the positive direction during the period from time t ₁ to t ₂ , the gate capacitance of the MOS transistor 5 is charged in the opposite polarity through the fourth winding n ₄ of the transformer 3. 3
Since there is double the gate capacitance when viewed from the third winding _n3 side, the gate drive waveform rises with the time constant of the resistor 12 and the double gate capacitance.
In order to reduce the time constant and achieve high-speed operation, the value of the resistor 12 may be reduced. But the time
During the period from t ₃ to t ₄ or from time t ₆ to t ₇ , both switch elements 9 and 10 are conductive, so that the first winding n ₁ and the third winding n of the transformer 3 ₃ is in a short-circuited state (no inductance exists), and the current flowing through the resistor 12 increases. Therefore, the smaller the value of the resistor 12, the more power consumption of the resistor 12 increases.

The present invention solves these drawbacks and makes it possible to drive a MOS transistor at high speed with low power consumption, and will be described in detail below with reference to the drawings.

FIG. 3 shows a first embodiment of the present invention, 20,
21 is a switch element, 22, 23, 24, 26 are
A NAND logic element, 25 is a timer circuit, and the beginning of the first winding _n1 of the transformer 3 (indicated by a black circle)
is at the drain of the switch element 20 (indicated by D),
The winding ends of the third winding n3 of the transformer ₃ are each connected to the drain of the switch element 21, and the winding ends of the first winding _n1 of the transformer 3 and the winding ends of the third winding n3 are connected to the drain of the switch element ₂₁ , respectively. The starting ends of the windings are commonly connected to the positive terminal of the DC power supply 11 through a resistor 12. Furthermore, input terminal 1
connected to one input of the NAND logic element 22;
The output of the NAND logic element 22 is the switch element 20
The input terminal 2 is connected to the input of one side of the NAND logic element 24, the output of the NAND logic element 24 is connected to the gate of the switch element 21, and the input terminals 1 and 2 are connected to the gate of the NAND logic element 23.
The output of the NAND logic element 23 is connected to the input of the timer circuit 25, the output of the timer circuit 25 is connected to the input of the NAND logic element 26, and the output of the NAND logic element 26 is connected to the input of the NAND logic element 26.
It is connected to the other inputs of NAND logic elements 22 and 23.

The operation will be explained below using the operation waveforms shown in FIG. In Fig. 4, A is the signal waveform of input terminal 1,
B is the signal waveform of the input terminal 2, E is the output waveform of the NAND logic element 23, F is the output waveform of the time limit circuit 25, G is the output waveform of the NAND logic element 22, and H is the output waveform of the NAND logic element 22.
The output waveform of the NAND logic element 24, I is the gate-source voltage waveform of the MOS transistor 5, and J is the
This is the gate-source voltage waveform of the MOS transistor 4. At time t ₁₁ , the signal at input terminal 1 becomes waveform A.
When the output of the NAND logic element 22 becomes a high level as shown in waveform G, the switch element 20 turns on. As a result, voltages shown in waveform I and waveform J are generated in the fourth winding n ₄ and the second winding n ₂ of the transformer 3, respectively, but the resistor 12 can be set to a sufficiently small value for reasons described later. Therefore, the time constant determined by the resistor 12 and the gate capacitances of the MOS transistors 4 and 5 is sufficiently small, the waveforms I and J change rapidly at time _t11 , and the MOS transistor 5 immediately changes to a conductive state. on the other hand,
The gate-source voltage of the MOS transistor 4 is in a cutoff state because only a reverse bias voltage is applied as shown in waveform J. When the signals at input terminals 1 and 2 become high level at time t ₁₂ ,
The output of the NAND logic element 23 becomes a low level as shown in waveform F. The timer circuit 25 generates a high level output signal for a predetermined period from time _t12 when the waveform E changes from high level to low level until time _t13 , at least until the MOS transistor 5 is completely cut off. As a result, a signal obtained by inverting the output signal of the time limit circuit 25 by the NAND logic element 26 (of course, since it is a 1-input NAND, an inverter circuit may be used) is applied to the other input terminals of the NAND logic elements 22 and 24, so the NAND logic The outputs of elements 22 and 24 go high at the same time, and switch elements 20 and 21 become conductive at the same time. At this time, similarly to the operation shown in Fig. 1, the winding start end (indicated by a black circle) of the first winding _n1 of the transformer 3 and the winding end end (indicated by a black circle) of the third winding are opposite to each other. Since the voltages are equal, transformer 3
All winding voltages become zero, equivalently creating a short-circuit condition. Therefore, the charges stored in the gate capacitances of MOS transistors 4 and 5 are rapidly discharged, similar to the operation described in FIG. 1, and MOS transistor 5 is quickly cut off. When the voltage at the input terminal 2 becomes low level at time _t14 , the switch element 21 becomes conductive, so the MOS transistor 4 becomes conductive, and the complementary circuit performs the same operation as described above.

Here, the difference between the set value of the resistor 12 and the circuit shown in FIG. 1 will be explained. In the case of the circuit shown in FIG. ₁ , _the switch element 9,
Both transistors 10 are conductive, and especially when the operating duty ratio for making the MOS transistor 4 or 5 conductive from time t ₁ to t ₃ (or from time t ₄ to t ₆ ) is small, from time t ₃ to t ₄ Since the ratio of the period up to this point increases, the average amount of current flowing through the resistor 12 increases. On the other hand, in the circuit shown in FIG. 3, the period from time t ₁₂ or t ₁₅ when the signal to cut off the MOS transistor 4 or 5 is generated to time t ₁₃ or t ₁₆ when the switch elements 20 and 21 are cut off simultaneously is the MOS transistor 4 or 5
Since current flows through resistor 12 only for a short period of time until the gate-source voltage of MOS transistor 4 or 5 becomes complete, the value of resistor 12 is reduced. Even in this case, the average amount of current flowing from the DC power supply 11 does not increase much.

Note that the time limit circuit 25 shown in FIG. 3 can be realized by a known monostable multivibrator circuit. FIG. 5 shows an example of the time limit circuit 25, in which 30 is an input signal terminal, 31 is an output signal terminal, 32, 33
is a resistor, 34 is a capacitor, 35 is a power supply terminal, 3
6 is a transistor, a capacitor 34 is connected between the input signal terminal 30 and the base of the transistor 36, resistors 33 and 32 are connected between the power supply terminal 35 and the base and collector of the transistor 36, respectively, and the collector of the transistor 36 is output. It is connected to the signal terminal 31. The input signal terminal 30 has
The output of the NAND logic element 23 is connected, and the output signal terminal 31 is connected to the input of the NAND logic element 26.

FIG. 6 shows operating waveforms for explaining the operation of FIG. 5, and K indicates the base voltage of the transistor 36. When the signal at the input signal terminal 30 falls at time t ₁₂ or t ₁₅ as shown in waveform E, the base voltage of the transistor 36 is driven to the negative side as shown in waveform K, and the transistor 36 is cut off, so that the output signal terminal 31 The signal rises as shown in waveform F. The current flowing through the resistor 33 causes the capacitor 34 to
As the transistor 36 is charged, the base voltage of the transistor 36 rises to the positive side, and when the base voltage reaches the voltage V _BE required to make the transistor 36 conductive at time t ₁₃ or t ₁₆ , the transistor 36 becomes conductive and outputs the output signal. The signal at terminal 31 falls as shown in waveform F. Therefore, as described above, in order to set the period necessary to sufficiently cut off the MOS transistor 4 or 5, the capacitor 34 or the resistor 33 in the time limit circuit shown in FIG. 3 may be set to a predetermined value.

As explained above, the first embodiment of the present invention shown in FIG.
In this embodiment, the value of the resistor 12 can be reduced with less power consumption, so compared to the conventional drive method, the MOS
The turn-on time of transistor 4 or 5 can be significantly improved.

FIG. 7 shows a second embodiment of the present invention, with 40,
41 is a NAND logic element, 42 is a switch element,
43 and 44 are diodes, and 45 is a resistor. Input terminals 1 and 2 are NAND logic elements 40 and 41, respectively.
connected to the input of NAND logic elements 40, 41
The outputs of the timer circuit 25 are connected to the gates of the switch elements 20 and 21, respectively, the output of the time limit circuit 25 is connected to the gate of the switch element 42 using a MOS transistor, and the source of the switch element 42 is connected to the negative terminal of the DC power supply 11. , the drain of the switch element 42 is connected to the cathodes of diodes 43 and 44 through a resistor 45, the anodes of the diodes 43 and 44 are connected to the drains of the switch elements 20 and 21, respectively, and the positive terminal of the DC power supply 11 is connected to the transformer 3. It is directly connected to the connection point of the first winding n ₁ and the third winding n ₃ without using a resistor.

The operation will be explained below using the operation waveforms shown in FIG. In Figure 8, A, B, E, F, I, J are the same symbols as explained in Figure 4, and L is
The output signal waveform of the NAND logic element 40, M is
This is the output signal waveform of the NAND logic element 41. When the signal at input terminal 1 becomes low level at time _t11 , the output of NAND logic element 40 becomes high level as shown in waveform L, and switch element 20 becomes conductive, so that the fourth winding _n4 of transformer 3 As shown in waveform I, a voltage equal to or higher than the gate threshold voltage V _th that makes MOS transistor 5 conductive is generated, and a negative voltage is generated in the second winding of transformer 3 in the direction that turns off MOS transistor 4, as shown in waveform J. voltage is generated. At this time, since the voltage at the input terminal 2 is at a high level as shown in waveform B, the output of the NAND logic element 41 is at a low level as shown in waveform M, and the switch element 21 is cut off. Unlike the circuit shown in FIG. 3, there is no resistor (resistance 12 in FIG. 3) in series with the DC power supply 11, so the voltage generated between the gate and source of the MOS transistor 5 rises steeply, and the MOS transistor operates at high speed. Turn on. When the signal at input terminal 1 rises at time _t12 , the output of NAND logic element 40 falls, and switch element 20 is cut off. At this time, the output of the time limit circuit 25 rises as shown in waveform F, similar to the operating waveform in FIG. 4, and makes the switch element 42 conductive. When the switch element 42 becomes conductive, a current In 1 flows from the DC power supply 11 through the first winding n ₁ of the transformer 3 and the diode 43, and a current In 1 flows from the DC power supply 11 through the first winding n ₁ of the transformer 3 and the third winding n 1 of the transformer 3 from the DC power supply 11.
The current flowing through the winding n ₃ and the diode 44
The sum of In ₂ is passed through the resistor 45 to the switch element 42.
flows from the drain to the source. At this time, the above current
In ₁ and In ₂ are equally connected to the first winding n ₁ and the third winding of transformer 3.
flows through winding n ₃ of transformer 3, the voltage at the beginning of the first winding n ₁ of transformer 3 (indicated by the black circle) and the voltage at the end of the third winding (opposite to the black circle) are equal. Nari, 3rd
Similar to the operation explained in the figure, MOS transistor 5
The gate-source voltage of MOS transistor 4 rapidly changes from a high level to zero, and the gate-source voltage of MOS transistor 4 rapidly changes from a negative polarity level to zero.
MOS transistor 5 turns off quickly.
When the output of the time limit circuit 25 becomes low level at time _t13 , the switch element 42 is cut off. time t ₁₄
When the signal at the input terminal 2 becomes low level, the MOS transistor 4 changes to a conductive state, and the complementary circuit operates as described above until time _t16 . time
If the currents In ₁ and In ₂ flow through the first winding n ₁ and the third winding n ₃ of the transformer 3 during the period from t ₁₂ to time t ₁₃ (or from time t ₁₅ to time t ₁₆ ), , cancels the magnetic flux of the transformer 3 and eliminates the inductance component for both windings n ₁ and n ₃ , so a resistor 45 is required to limit the current, similar to the resistor 12 in FIG. resistance 4
_The current flowing through _{resistor 12} in FIG _. Similar to the operation of , it is possible to drive a MOS transistor at high speed with low current consumption.

FIG. 9 shows a third embodiment of the present invention, in which 50 is a transformer and 51 and 52 are diodes. The first winding n ₁ , the second winding n ₂ , and the third winding of the transformer 50
n ₃ and the fourth winding n ₄ are the same as the windings of the transformer 3 used in FIG. 3 or FIG. 7, and a fifth winding n ₅ and a sixth winding n ₆ are provided. , the winding start end (indicated by a black circle) of the fifth winding n ₅ is connected to the drain of the switch element 42 through the diode 51, and the winding end (the opposite side to the black circle) of the sixth winding n ₆ is connected to the diode 52. The end of the fifth winding n ₅ and the beginning end of the sixth winding are both connected to the source of the switch element 42 .

Therefore, it is clear that the operation in which the MOS transistor 5 or 4 becomes conductive or non-conductive with respect to the signal applied to the input terminal 1 or 2 is the same as the operation shown in FIG. I will only explain. Now, the operating waveforms are the same as those shown in FIG. 8, and just before time _t12 , switch element 42 is cut off because its input is at a low level as shown in waveform F, and switch element 20 is cut off because its input is at a low level, as shown in waveform F. As shown in waveform L, since the voltage is at a high level and conductive, a positive voltage is generated in all the windings of the transformer 50 at the winding end (indicated by a black circle) with respect to the winding start end (indicated by a black circle). Input terminal 1 at time t ₁₂
When the voltage becomes low level, the output of the time limit circuit 25 becomes high level as shown in waveform F, so that the switch element 42 becomes conductive and the MOS transistors 5 and 4
transformer 5 until the gate-source voltage of transformer 5 becomes zero.
Current flows from the sixth winding n _{6 of} zero through the diode 52 to the switch element 42 . That is, M.O.S.
The charges stored in the gate capacitances of transistors 5 and 4 are discharged through the sixth winding n ₆ of transformer 50 by shorting diode 52 and switch element 42 . At this time, since there is no current limiting resistor for the discharge, the gate-source voltage of the MOS transistor 5 quickly becomes zero, and the MOS transistor 5
can turn off quickly. Immediately before time _t15 , the switch element 21 is conductive and the MOS transistor 4 is conductive, and a negative voltage is generated in all the windings of the transformer 50 at the end of the winding compared to the beginning of the winding. , switch element 4 at time t ₁₅
When 2 becomes conductive, MOS transistors 4 and 5
The discharge of the gate capacitance of the fifth winding of the transformer 50
This is performed by a series circuit of n ₅ , diode 51, and switch element 42. Also, at time t ₁₁
The switching speed when the MOS transistor 5 is turned on or when the MOS transistor 5 is turned on at time _t14 is high because it is the same as the circuit shown in FIG.

Note that the embodiment of the present invention described above has two
Although the method of driving the MOS transistors 4 and 5 alternately has been shown, the method can also be applied to the case of driving only one MOS transistor. That is, in the embodiments shown in FIGS. 3 and 7, if a signal is applied only to input terminal 1 and input terminal 2 is held at a high level, only MOS transistor 5 can be turned on or off. In the embodiment shown in FIG. 9, if a signal is applied only to input terminal 1 and input terminal 2 is held at a high level, even if the fifth winding _n5 of transformer 50 and diode 51 are removed, the MOS transistor It is possible to conduct or cut off only 5.

As explained above, in the present invention, in a circuit that drives a MOS transistor via a transformer, when the MOS transistor is cut off, an arbitrary winding of the transformer is operated for a predetermined period at least until the MOS transistor is cut off. Since the line voltage is maintained at a low voltage, the MOS transistor can be turned on and off quickly with low power consumption, making the present invention extremely useful.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional MOS transistor driving method, Figure 2 is an explanatory diagram of the operation of Figure 1,
3 is a circuit diagram showing the first embodiment of the present invention, FIG. 4 is an explanatory diagram of its operation, FIG. 5 is an example of the time limit circuit in FIG. 3, and FIG. 6 is an explanatory diagram of its operation. 7 is a circuit diagram showing a second embodiment of the present invention;
The figure is an explanatory diagram of its operation, and FIG. 9 is a circuit diagram showing a third embodiment of the present invention. 1, 2... Input terminal, 3, 50... Transformer,
4, 5...MOS transistor, 6, 7, 8...
Output terminal, 9, 10, 20, 21, 42... Switch element, 11... DC power supply, 12, 32, 3
3, 45...Resistor, 34...Capacitor, 36...
...Transistor, 22, 23, 24, 40, 41
... NAND logic element, 25 ... Time limit circuit, 30
...Input signal terminal, 31 ...Output signal terminal, 35
...Power terminal.

Claims (1)

[Claims] 1. A first winding of a transformer and a first switch element are connected in series, a third winding of the transformer and a second switch element are connected in series, and the first and second
Connect the switch to one end of the DC power supply, and
The winding and the third winding are wound in opposite directions, and the other ends of the first and third windings are connected to the other end of the DC power supply either directly or by connecting a resistor in series as desired. , in the driving method, the other winding of the transformer is connected to the gate electrode and the source electrode of the MOS transistor, and the MOS transistor is made conductive when the first and second switch elements are made conductive. drive each of the switches in
A NAND circuit is provided, and when one output of the input signal of the NAND circuit changes to a high level, the other input signal outputs a high level for a period until the MOS transistor is cut off, and the time when the input signal changes. The output of the timer circuit causes two windings of the transformer wound in opposite directions through the NAND circuit or switch element. 1. A method for driving a MOS transistor, comprising alternately conducting wires and maintaining a voltage between the windings at a low voltage.