JPH0226827U - - Google Patents
Info
- Publication number
- JPH0226827U JPH0226827U JP10604988U JP10604988U JPH0226827U JP H0226827 U JPH0226827 U JP H0226827U JP 10604988 U JP10604988 U JP 10604988U JP 10604988 U JP10604988 U JP 10604988U JP H0226827 U JPH0226827 U JP H0226827U
- Authority
- JP
- Japan
- Prior art keywords
- reference signal
- ring counter
- output
- circuit
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electric Clocks (AREA)
- Input From Keyboards Or The Like (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案に係るスイツチ装置の回路例を
示す図、第２図は第１図に示す回路例のタイムチ
ヤート図、第３図は従来のスイツチ装置の一例を
示す図である。
１０……基準信号発生回路、２０……リングカ
ウンタ、４０……スイツチ群、６０……ラツチ信
号発生回路、７０……レジスタ回路、８０……出
力回路。
FIG. 1 is a diagram showing a circuit example of a switch device according to the present invention, FIG. 2 is a time chart diagram of the circuit example shown in FIG. 1, and FIG. 3 is a diagram showing an example of a conventional switch device. DESCRIPTION OF SYMBOLS 10... Reference signal generation circuit, 20... Ring counter, 40... Switch group, 60... Latch signal generation circuit, 70... Register circuit, 80... Output circuit.
Claims (1)
ク入力とするリングカウンタと、 前記リングカウンタの各出力段に一端が接続さ
れるとともに、他端はリングカウンタからの出力
発生電位と異なる電位の電源側に接続された複数
個のスイツチと、 データ入力側にこのスイツチ群の全ての電源側
の一端が接続されるとともにクロツク入力として
前記基準信号が入力されるシフトレジスタを有す
るレジスタ回路と、 前記リングカウンタの出力段に接続され、リン
グカウンタの出力信号が最終段までシフトしたこ
とを検出してラツチ信号を出力するラツチ信号発
生回路と、 このラツチ信号を受けて前記シフトレジスタに
蓄積されたデータをラツチする出力回路と、 から成ることを特徴とするスイツチ装置。[Claims for Utility Model Registration] A reference signal generation circuit that generates a reference signal, a ring counter that receives the reference signal from the reference signal generation circuit as a clock input, and one end of which is connected to each output stage of the ring counter. At the same time, the other end is connected to multiple switches connected to the power supply side with a potential different from the output generation potential from the ring counter, and one end of the power supply side of all of these switches is connected to the data input side, and is used as a clock input. a register circuit having a shift register into which the reference signal is input; and a latch signal generation circuit connected to the output stage of the ring counter and outputting a latch signal upon detecting that the output signal of the ring counter has been shifted to the final stage. and an output circuit that receives the latch signal and latches the data stored in the shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10604988U JPH0226827U (en) | 1988-08-10 | 1988-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10604988U JPH0226827U (en) | 1988-08-10 | 1988-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226827U true JPH0226827U (en) | 1990-02-21 |
Family
ID=31339210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10604988U Pending JPH0226827U (en) | 1988-08-10 | 1988-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226827U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5093754A (en) * | 1973-12-21 | 1975-07-26 |
-
1988
- 1988-08-10 JP JP10604988U patent/JPH0226827U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5093754A (en) * | 1973-12-21 | 1975-07-26 |
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