JPH0345300U

JPH0345300U -

Info

Publication number: JPH0345300U
Application number: JP10639489U
Authority: JP
Priority date: 1989-09-11
Filing date: 1989-09-11
Publication date: 1991-04-25
Anticipated expiration: 2004-09-11
Also published as: JPH0749680Y2

Description

【図面の簡単な説明】第１図は、本考案のシフトレジスタの駆動回路
を示す回路図、第２図は、従来回路を示す回路図
、第３図は、第１図及び第２図のシフトレジスタ
内部における遅延型フリツプフロツプの構成を示
す回路図、第４図は、第１図及び第２図のクロツ
ク発生回路におけるクロツクの発生タイミングを
示すタイミングチヤートである。１……クロツク発生回路、５……シフトレジス
タ、６，７，９，１０……クロツクライン、１２
……第１の転送回路、１７……第２の転送回路、
３４，３５，３６，３７……インバータ。[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a shift register drive circuit of the present invention, Fig. 2 is a circuit diagram showing a conventional circuit, and Fig. 3 is a circuit diagram showing a drive circuit of a shift register of the present invention. FIG. 4, which is a circuit diagram showing the structure of a delay type flip-flop inside the shift register, is a timing chart showing the timing of clock generation in the clock generation circuit of FIGS. 1 and 2. 1... Clock generation circuit, 5... Shift register, 6, 7, 9, 10... Clock line, 12
...first transfer circuit, 17...second transfer circuit,
34, 35, 36, 37... Inverter.

Claims

[Claims for Utility Model Registration] (1) A first transfer circuit that inputs/outputs or holds data based on a first clock, and inputs data from the first transfer circuit based on a second clock. a shift register comprising a plurality of stages of delay flip-flops including a second transfer circuit for outputting or holding; a clock generation circuit for generating the first clock and the second clock; a first clock line for applying a clock based on the first transfer circuit to the first transfer circuit of the plurality of stages of the delay type flip-flop; and a first clock line for applying a clock based on the second clock to the second transfer circuit of the plurality of stages of the delay type flip-flop. a second clock line for applying voltage to a transfer circuit; and a shift register driving circuit, wherein the first clock line and the second clock line are connected from the output of the clock generation circuit to the output of the shift register. The first transfer circuit and the second transfer circuit further include a prohibition circuit that prohibits the first transfer circuit and the second transfer circuit from entering an input/output state simultaneously by the first clock and the second clock, respectively. Features a shift register drive circuit. (2) The clock generation circuit consists of a first OR gate to which an inverted reference clock is applied to one input terminal, and a second OR gate to which the reference clock is applied to one input terminal. , an output terminal of the first OR gate is connected to the first clock line and the other input terminal of the second OR gate, and an output terminal of the second OR gate is connected to the second input terminal of the second OR gate. 2. The shift register drive circuit according to claim 1, wherein the shift register drive circuit is connected to the lock line of the shift register and the other input terminal of the first OR gate. (3) The inhibiting circuit includes means for delaying the generation timing of the first clock and the second clock, and the inhibiting circuit includes means for delaying the generation timing of the first clock and the second clock, and the output terminal of the first OR gate and the other of the second OR gate. The shift according to claim 2, wherein the shifter is inserted between the input terminal and the output terminal of the second OR gate and the other input terminal of the first OR gate. Register drive circuit.