JPH02268342A - Rough simulation device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a rough simulation device that can automatically generate capacitance data and facilitates input data generation, and includes a first input means for inputting a logic circuit description, and a predetermined a second input means for inputting a capacitance calculation formula; an extraction means for extracting parameter information of an element from the logic circuit description; and a second input means for inputting a capacitance calculation formula; a conversion means for converting into a preset key variable, a calculation means for substituting the key variable into the capacity calculation formula and performing calculation, and a calculation result of the calculation means,
and generating means for generating a new logic circuit description by reflecting the logic circuit description.

[Industrial application field]

The present invention relates to a rough simulation device, and in particular,
This invention relates to a rough simile silon device that automatically generates capacity data and improves usability.

Electronic circuit simulations performed to confirm whether a designed circuit configuration satisfies desired electrical specifications are particularly useful for large-scale integrated circuits such as VLSI (
Very large 5cale integral
ion) is indispensable for the design.

[Conventional technology]

Generally, electronic circuit simulation involves two simulation processes: a rough simulation and then a final simulation. The present invention relates to rough simulation. Rough simulation is performed for the purpose of determining circuit constants immediately after logic design, while final simulation is performed for the purpose of determining circuit constants using a pattern verification system after determining a mask pattern.

[Problem to be solved by the invention]

However, in conventional rough simulations, the wiring capacitance required for simulation execution was calculated manually, which made it inconvenient to use from the perspective of facilitating the creation of input data. .

In other words, the input data when running a rough simulation is parameter information such as the type of elements that make up the circuit, element connection information (including node information), element size, resistance value, etc., and the capacitance value connected to the node. is not included in the original data. Therefore, the designer had to manually calculate this capacitance value and input the calculation results again.

Moreover, during rough simulation, trials are repeated until the optimal solution for the constants is obtained, so the more trials there are, the more the number of capacity calculations will be. Human errors will become unavoidable and may have a negative impact on the accuracy of the simulation.

The present invention was made in view of these problems, and
The purpose is to automatically generate capacity data and facilitate input data generation.

[Means to solve the problem]

In order to achieve the above object, the rough simulation device according to the present invention includes a first input means for inputting a logic circuit description, a second input means for inputting a predetermined capacity calculation formula,
an extraction means for extracting element parameter information from the logic circuit description; and a conversion means for converting the element parameter information extracted by the extraction means into key variables preset corresponding to the variables of the capacity calculation formula. , comprising a calculation means for substituting a key variable into the capacity calculation formula and performing an operation, and a generation means for generating a new logic circuit description by reflecting the calculation result of the calculation means in the logic circuit description. It consists of

[Effect]

In the present invention, capacity data for each node is automatically generated based on the logic circuit description and the capacity calculation formula, and a new logic circuit description is generated in which this capacity data is reflected in each node.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing an embodiment of a rough simulation device according to the present invention.

FIG. 1 is a diagram conceptually showing functional blocks of an embodiment, and some or all of the functions are realized by software. In FIG. 1, 1 is a first input means, 2 is a second input means, 3 is an extraction means, 4 is a conversion means,
5 is a calculation means, and 6 is a generation means.

FIG. 2 is a flowchart of the main part of the rough simulation processing program in this embodiment.

In FIG. 2, step P is a step for inputting a predetermined capacity calculation allowance (described later), and this step functions as the second input means 2. Step P2 is a step of encoding the input capacity calculation formula into a data structure suitable for simulation, and the coded capacity calculation formula is stored in an appropriate storage device.

Here, the capacitance calculation formula has a variable for each parameter of the element connected to the node of the logic circuit to be simulated, and by substituting the actual element parameter into this variable, it is possible to calculate the capacitance value of the node. This is a predetermined capacity calculation formula that can be used. Note that this easy calculation formula is input by the designer.

An example of the capacity calculation formula is shown in Attached Table 1.

In the example shown in Attached Table 1, the following formulas (1) to (2) are written in the FORTRAN language.

C0N=(5,2xWDN+21.5xNLN+1.1
73 L N) Xl0-' ・・・・・・■5IN
−(N+2 in β)” +WDNxlQ・・・・・・■3
2N = ((2x β1 ball + 4) +WDN) x 0.1
・・・・・・■ However, C0NXWDN, NLN, 5LNSSGN, WD
N, SIN, and S2N are each variables.

Examples of definitions for each variable are shown in Attached Table 2. In attached table 2,
For example, a variable called WDN (hereinafter referred to as a key variable) defines the total gate width value of transistors whose sources (or drains) are extraction nodes to be described later. Incidentally, the suffix N or P of each key variable indicates that N represents n channel and P represents p channel.

Also, CON, COP, 5INXSIP, 3 in Attached Table 2
2N and 32P correspond to the answer of the capacity to be determined.

That is, for example, the capacitance value for one node can be obtained by (CONxSINxS2N).

Step P is a step of inputting a logic circuit description (described later) representing the logic circuit designed by the designer.
This step functions as a first input means 1. A logic circuit "description" is a translation of a logic circuit into a language suitable for simulation, an example of which is shown in Appendix 3.

In Attached Table 3, ADBUFO is a circuit name given for convenience, and EXTNODE is, for example, a voltage [(Vcc).

VS3, ■. ), node names such as input/output (EA##Z5, EA##), QOI to QO4 are transistor (MOS in this example) names, TP and TN are transistor polarities (p-channel type or n-channel type) ). Then, on the right side of each polarity, the source (S)
, drain CD), gate) (G), and the node name connected to bulk (B) are written, and further to the right are the gate length (L-1, 2 μm in this example), gate width W (in this example , W=30 μm). In other words, the circuit (ADBUFO) described in this Appendix 3 has a QOI
A circuit consisting of four MOS transistors of ~QO4, whose nodes are VCCs vss, Vll, EA##
Z5, EA## and 01. Incidentally, it is recognized that the elements connected to node VCC, for example, are the source and bulk of QOI and the source and bulk of QO3. Figure 2 shows the circuit shown in Attached Table 3 (A
3 is a diagram showing a DBUFO) as a black box, and FIG. 3 is a diagram showing one MOS) transistor.

Step P4 is a step of extracting each node from the logic circuit description, and this step functions as extraction means 3. Nodes are extracted by extracting the nodes described in the source (S), drain (D), gate (G), and bulk (B) columns of each transistor in Attached Table 3. For example, looking at the QOI of ADBUFO, the source of this transistor is connected to node VCC, the drain is connected to node 01, the gate is connected to node EA##Z5, and the bulk is connected to node ■. ,It is connected to the.

Therefore, the extraction node is in this case vce,01,E
A total of 4, A##Z5 and VCC.

Step P is a step of calculating variables for each extracted node, that is, converting element parameters connected to the extracted nodes into corresponding key variables according to Appendix 2. This stamp functions as a converting means 4.

Step P6 is a step in which the key variable calculated in step P5 is substituted into the capacity calculation formula (see Appendix 1) to calculate the capacity value for each node, and this step functions as calculation means 5.

Step P7 is a step in which a new logic circuit description is generated by adding the capacitance value calculated in step Ph to the previous logic circuit description, and this step functions as the generation means 6.

Appendix 4 shows an example of a newly generated logic circuit description, and the data surrounded by a broken line is the capacity calculation result calculated in step P.

In this way, in this embodiment, the necessary capacitance data is automatically generated when a logic circuit description and a capacitance calculation formula are input. This eliminates the need for human intervention in capacitance calculations and facilitates input data generation. Simulation accuracy can be improved by avoiding human error.

In addition, the newly generated logic circuit description is transferred to step P3.
By inputting and repeating the subsequent steps P4 to P, it is possible to obtain an optimal solution for the circuit constants while automatically updating the capacitance connected to each node.

〔Effect of the invention〕

According to the present invention, capacity data can be automatically generated and input data generation can be facilitated.

[Brief explanation of drawings]

1 to 4 are diagrams showing an embodiment of the rough simulation device according to the present invention, FIG. 1 is a functional block diagram thereof, FIG. 2 is a flowchart of the main part of the simulation processing program, and FIG. is a diagram showing one circuit included in the logic circuit description, and FIG. 4 is a circuit diagram of a transistor included in the logic circuit description. 1...First input means,...Second input means,...Extraction means,...Conversion means,...Calculation Means, ... means of generation. 0PII! RATION Capacity calculation formula description example attached table Key variables - list logic circuit description example attached table Newly generated logic circuit description example attached table Figure (S) Circuit diagram of the transistor included in the logic circuit description of one embodiment Figure 4

Claims (1)

[Scope of Claims] A first input means for inputting a logic circuit description, a second input means for inputting a predetermined capacity calculation formula, and an extraction means for extracting element parameter information from the logic circuit description. a conversion means for converting parameter information of the element extracted by the extraction means into a key variable set in advance corresponding to a variable in the capacitance calculation formula; and a conversion unit for substituting the key variable into the capacitance calculation formula to perform an operation. A rough simulation device comprising: a calculation means; and a generation means for generating a new logic circuit description by reflecting the calculation result of the calculation means on the logic circuit description.