JPH02268482A - Manufacture of buried semiconductor laser element - Google Patents

Manufacture of buried semiconductor laser element

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Publication number
JPH02268482A
JPH02268482A JP9046389A JP9046389A JPH02268482A JP H02268482 A JPH02268482 A JP H02268482A JP 9046389 A JP9046389 A JP 9046389A JP 9046389 A JP9046389 A JP 9046389A JP H02268482 A JPH02268482 A JP H02268482A
Authority
JP
Japan
Prior art keywords
layer
semiconductor laser
gaas
substrate
mesa stripe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9046389A
Other languages
Japanese (ja)
Inventor
Kunio Matsubara
松原 邦雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP9046389A priority Critical patent/JPH02268482A/en
Publication of JPH02268482A publication Critical patent/JPH02268482A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To elevate the crystal property of a current constriction layer so as to manufacture a laser element by forming a mesa stripe on a GaAs substrate, and thereon growing an epitaxial layer for double-hetero semiconductor laser, and growing a current constriction layer without using selective growth. CONSTITUTION:Etching is done using phosphoric acid etchant with the photoresist as a mask in the direction of <011> on the face (100) of an n-GaAs substrate 1 so as to form a mesa stripe 12. Next, the substrate 1 is carried in a MOCVD device, and epitaxial growth is performed, whereby an n-clad layer 2, a p-active layer 3, a p-clad layer 4, and a p contact layer are formed, in order on the mesa stripe 12. Subsequently, an Al0.45Ga0.55As layer 7 of high resistance is grown, and further an n-GaAs current constriction layer 6 is grown. Next, the substrate 1 is taken out of the MOCVD device, and the topside of the active layer is etched with the photoresist, etc., as a mask so as to expose the p contact layer 5. By performing wafer process, a semiconductor layer element is completed.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はGaAs−A I GaAS系ダブルへテロ埋
め込み型半導体レージ”素子の14造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a GaAs-A I GaAS double hetero embedded semiconductor laser device.

[従来の技術] 従来、GaAs−A I GaAs系ダブルへテロ埋め
込み型半導体レーザ素子として、第3図に承りようなも
のが提案されている。
[Prior Art] Conventionally, a GaAs-A I GaAs double-hetero buried semiconductor laser device as shown in FIG. 3 has been proposed.

この第3図において、1はn−Q&AS基板、2はn−
AIQaASクラッド層、 0、45   0.55 3はp−AI    Ga    AS活性層、4は0
.08   0.92 p−△l    Ga    Asクラッド層、5は0
.45   0.55 p−GaAsコンタクト層、6はn−GaAS電流狭窄
層10及び11は電極である。このダブルへテロ埋め込
み型半導体レーザ素子は一般のダブルへテロ半導体レー
!ア素子では得られない優れた特性をT=J シている
。すなわら、活性領域3が比較的混晶比の大なるn−A
lGaAsクラ 0.45   0.55 ラド層2及びp−AI    (3a    Asクラ
0.45   0.55 ラド層4に囲まれた構造であり、ざらに電流狭窄層6に
よって活性領域3の一部分にしか電流が流れず、発振し
きい値電流が低減し、また発振モード(持・に横モード
)の電流変化に対する安定性が向上づ゛る。さらに電流
狭窄層6の材料を選ぶことにより、電流狭窄層6が光吸
収層となり、高出力化が可能になる。
In this Figure 3, 1 is an n-Q&AS board, 2 is an n-
AIQaAS cladding layer, 0, 45 0.55 3 is p-AI Ga AS active layer, 4 is 0
.. 08 0.92 p-Δl Ga As cladding layer, 5 is 0
.. 45 0.55 p-GaAs contact layer 6, n-GaAS current confinement layers 10 and 11 are electrodes. This double hetero embedded type semiconductor laser device is a general double hetero semiconductor laser! T=J has excellent characteristics that cannot be obtained with A elements. In other words, the active region 3 has n-A with a relatively large mixed crystal ratio.
It has a structure surrounded by the lGaAs layer 2 and the p-AI (3a) Rad layer 4, and only a part of the active region 3 is roughly surrounded by the current confinement layer 6. No current flows, the oscillation threshold current is reduced, and the stability against current changes in the oscillation mode (main and transverse modes) is improved.Furthermore, by selecting the material for the current confinement layer 6, the current confinement is reduced. Layer 6 becomes a light absorption layer, making it possible to achieve high output.

このようにGaAs−A I GaAs系ダブルへテロ
埋め込み型の半導体レーリ“素子は安定で高出力な光源
となるため、光情報伝送及び光情報処理用光源とじで4
1望視されている。しかし、これらの特徴を発揮しえる
素子を1qる歩留りは極めて低く、また/↑命も短いの
で、工業的に問題を含んでい lこ 。
In this way, the GaAs-AI GaAs double-hetero embedded type semiconductor Rayleigh device becomes a stable and high-output light source, so it can be used as a light source for optical information transmission and optical information processing.
1 telescope. However, the yield of producing 1q of devices that can exhibit these characteristics is extremely low, and the lifespan is short, so this poses an industrial problem.

この第3図例の埋め込み型半導体レーザ索子の製造方法
とし第4図に示す方法が用いられている。
The method shown in FIG. 4 is used as a method of manufacturing the embedded type semiconductor laser cable shown in FIG. 3.

まず、n−=GaAsJiGaAs基板1上 0.45
Asクラッド層4(キレ9フ1度1 x 1018/ 
cm3膜厚1=5μm> 、D−GaAsコンタク1〜
層5(キiy リフ 濃度1×1018/Cm3、膜厚
0.5μm)を順次MOCVD法を用いて形成し、その
後、S + 02層12をスパッタ法によりpコンタク
ト層5上に形成し、最終的に電流通路を形成づべき部分
上にスlへライブ状のエツチングマスク8を周知の技術
によって付希覆る(第4図(a))。
First, n-=GaAsJiGaAs substrate 1 0.45
As cladding layer 4 (9 degrees sharp 1 degree 1 x 1018/
cm3 film thickness 1 = 5 μm>, D-GaAs contact 1~
Layer 5 (key concentration: 1 x 1018/Cm3, film thickness: 0.5 μm) is sequentially formed using the MOCVD method, and then an S + 02 layer 12 is formed on the p contact layer 5 by sputtering. A slit-like etching mask 8 is applied over the portion where a current path is to be formed using a well-known technique (FIG. 4(a)).

次に、SI OZ 層12中、エツチングマスク8によ
って保護されていない部分をまずバッファーフッ酸を用
いて除去し、次に例えばリン酸系エツチング液を用いて
pコンタクト層5中エツチングマスク8によって保護さ
れていない部分を除去し、更に続けてpクララド層4の
一部を所定の厚さを残して除去した後、エツチングマス
ク8を除去刃る(第4図(b)。このようにしてス1〜
ライブを形成した基板を再度MOCVDI置内に搬入し
、S ! 02 層12を選択成長用のマスクとしてn
G a A S電流狭窄層6を選択埋め込み成長法を用
いて成長さける(第4図(C))。
Next, the portions of the SI OZ layer 12 that are not protected by the etching mask 8 are first removed using buffered hydrofluoric acid, and then the portions of the p-contact layer 5 that are not protected by the etching mask 8 are removed using, for example, a phosphoric acid-based etching solution. After removing the unetched portions and subsequently removing a part of the p-Clarad layer 4 leaving a predetermined thickness, the etching mask 8 is removed (FIG. 4(b). In this way, the etching mask 8 is removed. 1~
The substrate on which the live pattern was formed was carried into the MOCVDI equipment again, and S! 02 layer 12 as a mask for selective growth
The G a AS current confinement layer 6 is grown using a selective filling growth method (FIG. 4(C)).

そして、S + 02m12をバッフフッフッ酸で除去
づることにより埋め込み型半導体レーザ素子用のエピタ
キシャル層が1qられる(第4図(d))。
Then, 1q of epitaxial layers for a buried semiconductor laser element are obtained by removing S+02m12 with buffed fluoric acid (FIG. 4(d)).

その後、通常のレー(アダイオード製造プロレスを用い
ることによって、第3図に示した様な埋め込み型半導体
レー沓ア素子を1qることができる。
Thereafter, by using a normal laser diode manufacturing process, it is possible to manufacture 1q of embedded semiconductor laser elements as shown in FIG.

[発明が解決しようとする課題1 しかしながら、上述した方法で埋め込み型半導体レー畳
ア素子を製造する場合、以下に述べる問題点がおった。
[Problem to be Solved by the Invention 1] However, when manufacturing an embedded semiconductor layer element by the method described above, the following problems occurred.

まず、電流狭窄層6を形成するための選択埋め込み成長
が難しく、一部子結晶が8102層12上にイ・」着し
、マスク材の除去が困難になり、生産性が低かった。ま
た、第1のエピタキシャル成長終了後、エツチングを行
い、第2のエピタキシャル成長を行う際、pクララド層
4が一度大気にざらされて酸化され、その影響で第2の
エピタキシャル層の膜質が劣り、一部電流が電流狭窄層
6内を通り、発娠しきい値を高くしていた。
First, selective filling growth for forming the current confinement layer 6 was difficult, and one molecular crystal was deposited on the 8102 layer 12, making it difficult to remove the mask material and resulting in low productivity. Furthermore, when etching is performed after the first epitaxial growth is completed and second epitaxial growth is performed, the p-Clarad layer 4 is once exposed to the atmosphere and oxidized, and as a result, the film quality of the second epitaxial layer is inferior, and some The current passed through the current confinement layer 6, increasing the triggering threshold.

ざらに、5102層12とGaAsの膨張係数が異なる
ために、第2のエピタキシャル成長を行う際に、活性層
3内にストレスによる転位が生じ、この転位が素子の寿
命を縮める原因となっていた。
In general, because the expansion coefficients of the 5102 layer 12 and GaAs are different, stress causes dislocations in the active layer 3 during the second epitaxial growth, and these dislocations shorten the life of the device.

[課題を解決するための手段] 本発明はGaAs基板にエツチングによりメサストライ
プを形成し、このメ(ノストライプーヒに通常のダブル
l\テロ半導体し−ザ用エピタキシ(・ル層の成長を行
い、さらに続いて選択成長を用いずに電流狭窄層を成長
さけるものである。
[Means for Solving the Problems] The present invention involves forming a mesa stripe on a GaAs substrate by etching, growing a normal double-layer epitaxy layer on the mesa stripe, and further Subsequently, a current confinement layer is grown without using selective growth.

[作用] 本発明を用いると、選択成長を用いずに埋め込み型半導
体レー沓ア素子が製造できるため、以下の特徴がおる。
[Function] By using the present invention, a buried type semiconductor laser device can be manufactured without using selective growth, so that it has the following features.

まず、s io2mの形成及び除去の工程が削減される
。また、電流狭窄層の成長を連続して行うため、表面が
酸化されでいない領域上への成長となり、電流狭窄層の
結晶性が向上しリーク電流がなくなる。さらにSiO2
層を形成せずに成長を行うため、S ! 02 ’14
2上への多結晶の付着という事態が回避され、歩留りが
向上するとともに、膨張係数の違いによるス1〜レスが
生じず、このため、活性層内に転位が発生しなくなり、
寿命も延びる。
First, the steps of forming and removing sio2m are eliminated. Furthermore, since the current confinement layer is grown continuously, it grows on a region where the surface is not oxidized, improving the crystallinity of the current confinement layer and eliminating leakage current. Furthermore, SiO2
Because growth occurs without forming layers, S! 02 '14
This avoids the deposition of polycrystals on the active layer, improves yield, and eliminates the occurrence of scratches due to differences in expansion coefficients, which prevents dislocations from occurring within the active layer.
It also extends your lifespan.

[実施例] 以下、第1図を参照して本発明の一実施例につき説明す
る。
[Example] Hereinafter, an example of the present invention will be described with reference to FIG.

まず、n −Q a A S %板1(キャリアIaf
311(IX1018Cm3) ノ(100)面上17
) <011 >方向ニフォトレジトとをマスクとして
リン酸系エツチング液を用いてエツチングを行い、メ]
ノストライプ(リッジ)12を形成する(第1図(a)
)。この時、エツチングは基板表面から2.5μm以上
の深さまで行うJ、うにする。
First, n - Q a A S % plate 1 (carrier Iaf
311 (IX1018Cm3) 17 on (100) surface
) Etching is performed using a phosphoric acid-based etching solution using the <011> direction photoresist as a mask, and
Form a stripe (ridge) 12 (Fig. 1(a)
). At this time, etching is performed to a depth of 2.5 μm or more from the substrate surface.

次にこのn −G a A S B板1をMOCVDH
置に搬入し、前述したのと同様のエピタキシャル成長を
行い、メ1ノ°ストライプ12上にn−クラッド層2、
p−活性層3、p−クラッド層4及び012991層5
を順次形成する。ここに、これら「)−クラッド層2、
活性層3、p−クラッドM4及び012991層5は仝
休として断面略二等辺三角形になる(第1図(b))。
Next, this n-G a A S B board 1 is MOCVDH
The same epitaxial growth as described above is carried out to form an n-cladding layer 2 on the square stripe 12.
p-active layer 3, p-cladding layer 4 and 012991 layer 5
are formed sequentially. Here, these ")-cladding layer 2,
The active layer 3, the p-cladding M4, and the 012991 layer 5 have a substantially isosceles triangular cross section (FIG. 1(b)).

この三角形の面ばn(コaAs基板1と常に54.7°
になり、−例として活性層幅3を3μmにするためには
、メザストライプ120幅を5μmにすればよい。また
、メサス1〜ライブ12以外の部分にもエピタキシャル
層が成長するが、次のエピタキシャル成長でコンタクト
層上に高抵抗層を成長ざけるので問題はない。
This triangular surface n (always 54.7° with the core aAs substrate 1)
For example, in order to make the active layer width 3 3 μm, the width of the meza stripe 120 should be 5 μm. Further, although the epitaxial layer grows in areas other than the mesus 1 to live 12, there is no problem because a high resistance layer is grown on the contact layer in the next epitaxial growth.

の成長はソリストライプ12上のp−活性層3がら上方
に所定位買だけ離れた所で終らせ、ざらにr〕GaAS
電流狭窄層6を成長さける(第1図(C))、。
The growth of GaAS was terminated at a predetermined distance above the p-active layer 3 on the soristripe 12, and the growth of GaAS
Avoid growing the current confinement layer 6 (FIG. 1(C)).

次にエピタコ1−シトル基板をMOCVD装置から取り
出し、活性領域上をフォ1へレジスト等をマスクにして
エツチングを行い、012991層5を露出さける(第
1図(d))。
Next, the epitaxial 1-sittle substrate is taken out from the MOCVD apparatus, and etching is performed on the active region using a resist or the like as a mask to avoid exposing the 012991 layer 5 (FIG. 1(d)).

以後は一般に用いられている半導体レーザ素子のウェハ
ープロレスを行って半導体レーザ素子を完成さける(第
1図(e))。
Thereafter, a commonly used wafer wrestling process for semiconductor laser devices is performed to complete the semiconductor laser device (FIG. 1(e)).

ここに、本実施例により製造した埋め込み型半導体レー
デ素子の電流−光出力特性を第2図に示す。第4図従来
例で製造した埋め込み、型半導体シー1ア素子(第3図
例〉と比べて発振しきい値が10%稈度低くなったのが
確認できた。これは良好な電流狭窄層が形成されたため
、活性層3を流れる電流密度か増加したためと考えられ
る。
FIG. 2 shows the current-optical output characteristics of the embedded semiconductor radar device manufactured according to this example. It was confirmed that the oscillation threshold value was 10% lower than that of the buried type semiconductor SIA element manufactured in the conventional example in Figure 4 (example in Figure 3). It is thought that this is because the current density flowing through the active layer 3 increased due to the formation of .

また、本実施例による製造方法と第4図に示す従来技術
による製造方法とで良品率を調べてみた。
In addition, the yield rate was investigated between the manufacturing method according to this embodiment and the manufacturing method according to the prior art shown in FIG.

本実施例を用いると基板全体から良品が試作できたのに
対し、従来方法では一部8102層、12上に多結晶が
付着し良品が試作できない箇所があった。
Using this embodiment, a good product could be prototyped from the entire substrate, whereas in the conventional method, polycrystals adhered to some of the 8102 layers and 12, making it impossible to make a good product.

さらに得られた良品について寿命試験を行ったところ、
従来の製造方法に対し、規定時間以上発掘を続Cプでい
る良品率も15%以上多くなった。これは5ho2とG
aAsとの膨張係数の違いによって生じる転位の数が5
ro2層12を用いないために無くなったためだと考才
られる。
Furthermore, when we conducted a life test on the obtained good products, we found that
Compared to conventional manufacturing methods, the rate of non-defective products that can be continuously excavated for longer than the specified time has increased by more than 15%. This is 5ho2 and G
The number of dislocations caused by the difference in expansion coefficient from aAs is 5.
It is thought that this is because the RO2 layer 12 was not used, so it disappeared.

[発明の効果] このJ、うに本発明を用いると、選択成長を用いずに埋
め込み型半導体レーザ素子が製造できるため、工数が削
減されるとともに電流狭窄層の結晶性が向上して発振し
きい値が低減される。ざらに熱膨張係数の違いによるス
トレスが生じないため、寿命も延びる。
[Effect of the invention] By using the present invention, a buried semiconductor laser device can be manufactured without using selective growth, which reduces the number of man-hours and improves the crystallinity of the current confinement layer to improve the oscillation threshold. value is reduced. The lifespan is also extended because there is no stress caused by differences in thermal expansion coefficients.

【図面の簡単な説明】[Brief explanation of drawings]

第′1図(a)〜(0)は本発明による埋め込み型半導
体ジー11素子の製造方法の工程を示す断面図、第2図
(31第1図例で製造した半導体レーザ素子の電流−光
出力特性図、第3図は従来のGaAS−A I GaA
S系ダブルへテロ埋め込み型半導体レーザ素子を示す断
面図、第4図(a)〜(d)は第3図例を製造Jる工程
を示す断面図である。 1・・・n−G、a A 5塁板、2・・・「)クラッ
ド層、3・・・p活性層、4・・・pクラッド層、5・
・・p]ンタク1〜M、6・・・電流狭窄M、7・・・
高抵抗AlGaAs1ffl、12−3.102 層第 ] 図 (その1) 第 ] 区 (その2) 電流(mA) 第 図 第 図 7/−8工ツチングマスク層 「12 篤 又 (その1) 第 図 (その2)
Figures 1 (a) to (0) are cross-sectional views showing the steps of the manufacturing method of the embedded semiconductor laser device according to the present invention, and Figure 2 (31) is a cross-sectional view showing the steps of the manufacturing method of the embedded semiconductor laser device according to the present invention. Output characteristic diagram, Figure 3 is the conventional GaAS-A I GaA
4(a) to 4(d) are cross-sectional views showing the process of manufacturing the example shown in FIG. 3. FIGS. 1... n-G, a A 5th base plate, 2... cladding layer, 3... p active layer, 4... p cladding layer, 5...
・・p] Ntaku 1-M, 6... Current constriction M, 7...
High resistance AlGaAs1ffl, 12-3.102 Layer] Figure (Part 1) Section (Part 2) Current (mA) Part 2)

Claims (1)

【特許請求の範囲】[Claims] GaAs基板の(100)面上に〈011〉方向へメサ
ストライプを形成する工程と、Al_xG_a_1_−
_xAs第1クラッド層、Al_yGa_1_−_yA
s活性層、Al_xGa_1_−_xAs第2クラッド
層、GaAsコンタクト層をメサストライプ上に成長さ
せる工程と、高抵抗Al_zGa_1_−_zAs層で
前記活性層を埋め込む工程と(但しx≧z>y)、高抵
抗Al_zGa_1_−_zAs上に電流制限層を成長
させる工程とを有することを特徴とする埋め込み型半導
体レーザ素子の製造方法。
A step of forming a mesa stripe in the <011> direction on the (100) plane of the GaAs substrate, and
_xAs first cladding layer, Al_yGa_1_-_yA
s active layer, Al_xGa_1_-_xAs second cladding layer, and GaAs contact layer on the mesa stripe; burying the active layer with a high-resistance Al_zGa_1_-_zAs layer (where x≧z>y); 1. A method for manufacturing a buried semiconductor laser device, comprising the step of growing a current limiting layer on Al_zGa_1_-_zAs.
JP9046389A 1989-04-10 1989-04-10 Manufacture of buried semiconductor laser element Pending JPH02268482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9046389A JPH02268482A (en) 1989-04-10 1989-04-10 Manufacture of buried semiconductor laser element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9046389A JPH02268482A (en) 1989-04-10 1989-04-10 Manufacture of buried semiconductor laser element

Publications (1)

Publication Number Publication Date
JPH02268482A true JPH02268482A (en) 1990-11-02

Family

ID=13999300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9046389A Pending JPH02268482A (en) 1989-04-10 1989-04-10 Manufacture of buried semiconductor laser element

Country Status (1)

Country Link
JP (1) JPH02268482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111382A (en) * 1990-08-30 1992-04-13 Sharp Corp Manufacture of semiconductor laser device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111382A (en) * 1990-08-30 1992-04-13 Sharp Corp Manufacture of semiconductor laser device

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