JPH02268574A - Character signal generation circuit - Google Patents

Abstract

PURPOSE:To insert a character even to the variable speed reproducing signal of a VTR without accompanying by perpendicular fluctuation by using a vertical blanking signal as a vertical synchronizing signal, and a signal generated at a phase locked loop as a horizontal synchronizing signal. CONSTITUTION:The vertical blanking signal V-BLK generated from the rotary phase detecting pulse of a rotary head drum in a video tape recorder is used as the vertical synchronizing signal, and also, the signal generated at the phase locked loop(PLL) 9 in which the horizontal synchronizing signal of a reproducing video signal is set as phase reference is used as the horizontal synchronizing signal. Thus, the vertical blanking signal V-BLK generated from a PG pulse is used as the vertical synchronizing signal. Thereby, a stable vertical synchronizing signal can be obtained without missing. Also, since the signal generated at the PLL circuit 9 where the horizontal synchronizing signal SYNC of the reproducing video signal is set as the phase reference is used as the horizontal synchronizing signal, the signal with a constant cycle can be obtained by the PLL circuit even when disturbance due to missing exists in the horizontal synchronizing signal SYNC.

Description

[Detailed Description of the Invention] [Industrial Application Field] In a video signal recording and reproducing device, this invention relates to a character signal generating circuit that outputs characters and the like in synchronization with the video signal along with the video signal. The present invention relates to a character signal generating circuit that can display characters, etc. without any image.

[Summary of the invention]

In a character signal generation circuit that generates a character signal in response to an address signal formed based on a vertical synchronization signal and a horizontal synchronization signal, the vertical synchronization signal is generated from a rotational phase detection pulse of a rotating head drum of a video tape recorder (VTR). A phase-locked loop (PLL) that uses the generated vertical blanking signal and uses the horizontal synchronization signal of the reproduced video signal as the horizontal synchronization signal as a phase reference.
A character signal generation circuit that can insert characters into a VTR's variable speed playback signal without vertical fluctuation by using a signal generated by the .

[Conventional technology]

2. Description of the Related Art A video signal recording and reproducing apparatus such as a video tape recorder (VTR) is sometimes equipped with a character signal generation circuit for superimposing characters such as letters on a video signal. In such a character signal generation circuit, a character signal is generated in synchronization with a vertical synchronization signal (V-5YNC) and a horizontal synchronization signal (H-SYNC) of a video signal. An example of a conventional character signal generation circuit will be described with reference to FIGS. 3 and 4. As shown in Figure 3, the reproduced video signal (PB VIDEO)
A synchronization separation circuit (SYNC5EP) extracts the composite synchronization signal a shown in FIG. As a result, a character signal synchronized with V-SYNC and H-5YNC is obtained. First, V-SYNC uses a signal C obtained from a monostable multipipe rake (MMV) 3 and a D flip-flop (D-FF) 2. That is, from the rising edge of the equalization pulse inserted into the composite synchronization signal a at intervals of η of one horizontal period, the interval is at least wider than the width of the equalization pulse, for example, by about %.
A signal b@y4HMMV that rises at a time shifted by H (IH is one horizontal period) is obtained, and a vertical blanking signal is extracted by a D flip-flop 2 using the signal S as a clock to obtain a signal C.

Next, 1l-5YNC is a % killer (ILL) that turns off one out of every two equalization pulses and takes out the pulse for each IH.
ER) through the circuit 4, obtain the signal e, and input the signal e to H-
Character display controller 5 as 5YNC
I am sending it to Character display controller 5
has a data memory for character display, and by inputting data specifying the memory address, display position, etc. of a character from the outside, it outputs a character signal for inserting a predetermined character, etc. at a predetermined position. ing. For example, the character display position is H based on V-SYNC.
This is done by counting -5YNC or the like. A character signal is inserted into the reproduced video signal by an insertion circuit (not shown).

In the conventional example described above, the reproduction signal (
Normal playback signal) or a video signal obtained without passing the input signal through an electromagnetic conversion system etc. (If an EE double signal is input, a synchronization signal with no omissions (V-5YNC and H-3YNC)
) is obtained. However, during variable speed playback of slots, stills, cues, reviews, etc., the magnetic head does not trace the recording track correctly and crosses the gart band or recording track, resulting in a decrease in the playback output and the formation of noise bands on the screen. When the noise band generation timing and the vertical synchronization signal in the reproduced video signal overlap, V-5YNC fluctuates or is missing, and the H-SYNC position within one field also fluctuates, with V-SYNC being the standard. There has been a problem in that the display position of the characters that determine the display position on the screen fluctuates, particularly in the vertical direction, and sometimes disappears.

On the other hand, according to the technique disclosed in JP-A-62-150979, when the period of the synchronization signal of the video signal is abnormally short, the vertical synchronization signal with the abnormally short period is used for superimposition. This prevents the signal from entering the internal circuits that perform processing (such as computer circuits) to accommodate phase shifts in the synchronization signal caused by channel switching on a television receiver, etc. Even with this technique, although it is possible to remove the synchronization signal having an abnormally short period, it cannot deal with the loss of the synchronization signal or the variation in the interval.

On the other hand, as a countermeasure against disturbances in the monitor image of the playback signal (ST ILL/JOG playback signal) during variable speed playback, a method using regularly generated pseudo synchronization signals is known. In the disclosed pseudo synchronization signal generation circuit, the rotational phase detection pulse (P
C pulse) to obtain a pseudo synchronization signal. In a VTR, the rotation of the rotary head drum and the vertical synchronization signal of the reproduced video signal are controlled to have a constant relationship. Therefore, by obtaining a pseudo synchronization signal from the PG pulse obtained by the rotation of the rotary head drum, the reproduction This is because even if there is a drop in the vertical synchronization signal of the video signal, a reproduced video without any disturbance can be obtained. However, there has been no technique for controlling character signal generation for inserting characters into a video signal that has similar effects.

Therefore, even if the image based on the reproduced video signal is stably displayed on the screen, there is a problem that the inserted characters are not stable.

[Problems to be Solved by the Invention] A character signal generation circuit that solves various problems in the prior art and makes it possible to insert characters such as letters into a variable speed reproduction signal and display them on the screen without any vertical fluctuations. The challenge is to obtain.

[Means to solve the problem]

In the present invention, in a character signal generation circuit that generates a character signal in response to an address signal formed based on a vertical synchronization signal and a horizontal synchronization signal, the vertical synchronization signal is generated by a rotating head drum of a videotape type coder (VTR). A vertical blanking signal made from a rotational phase detection pulse (PC pulse) of A character signal generation circuit characterized in that it is used.

[Effect]

Obtain an address signal indicating a character display position by means of an address signal formed based on vertical and horizontal synchronization signals, for example, by counting the number of horizontal synchronization signals with the vertical synchronization signal as a reference, In a character signal generation circuit that generates a character signal, V
If the vertical and horizontal synchronization signals can be stably supplied without any loss or fluctuation during variable-speed playback of the TR, it is possible to generate character signals without fluctuations, and this also applies to the reproduced signal during variable-speed playback. Character signals without fluctuation can be inserted.

In the present invention, since the vertical blanking signal generated from the PC pulse is used as the vertical synchronizing signal, it is possible to obtain a stable vertical synchronizing signal without any dropout.

Further, as the horizontal synchronization signal, a PLL using a horizontal synchronization signal (PB H-SYNC) of a reproduced video signal as a phase reference.
Since the signal generated by the circuit is used, the PB H-
Even if there is a disturbance such as a drop in SYNC, a signal with a constant period can be obtained by the PLL circuit.

〔Example〕

The present invention will be explained in detail according to FIGS. 1 and 2.

Fig. 1 shows a block diagram of an embodiment of the present invention, Fig. 2 shows a timing chart of signal waveforms corresponding to each part in Fig. 1, and parts corresponding to the conventional example in Figs. 3 and 4 are the same. Numbers and codes are given.

First, focusing on the vertical synchronizing signal input terminal V-IN of the character display controller 5, the following configuration is different from that of the conventional block diagram shown in FIG. That is, a V-BLK inputs a vertical blanking signal (V-BLK) generated by the technique disclosed in Japanese Patent Application Laid-Open No. 56-31283 from the rotational phase detection pulse of the rotating head drum.
It has an IN terminal 6, and a monostable multivibrator (
MMV) 7 and a signal C obtained from the same e<D flip-flop (D-FF) 2 as in the conventional example. The difference is that the vertical synchronization signal is supplied to V-IN of the character display controller 5.

Next, paying attention to the horizontal synchronizing signal input terminal H-IN of the character display controller 5, the following configuration is different from that of the conventional block diagram shown in FIG. That is, the signal e output from the AH killer (KILLER) circuit 4
Instead of sending the signal directly to H-IN, the phase-locked loop (PL
L) A horizontal synchronizing signal i is obtained from the output signal g of the PLL 9- by a monostable multi-vibration break (MMV) 10 through the H-IN, and is supplied to the H-IN.

Next, the operation of this embodiment will be explained based on FIGS. 1 and 2. First, connect the 5YNCIN terminal 1 to EE mode (a mode that emits from the electrical system and reaches the electrical system without passing through the electromagnetic conversion system)
When a composite synchronization signal separated from the input video signal of is inputted, a vertical synchronization signal C separated from the signal a is inputted to one input terminal of the OR circuit 8. At this time, Sea BL
Since there is no input to KIN when the rotary head is not rotating, signal C is sent to V-IN.

If the rotary head is rotating even in the EE mode, the signal d is supplied to the other input terminal of the OR circuit 8. Although the polarity of the signals is not strictly shown in FIGS. 1 and 2, the OR circuit 8 is configured to give priority to the signal d over the signal C. Therefore, when the rotary head is rotating, signal d is supplied to V-IN with priority regardless of the presence or absence of signal C. Note that signal d is a wider pulse than signal C, and its terminal rise point is slightly later than that of signal C (for example, y
2H), the OR circuit 8 ensures that the signal d takes priority even if signal C fluctuates. Since the rad drum is rotating both during normal playback and during variable speed playback, the signal d takes priority and is input to the V-IN of the character display controller 5.
By the way, in a VTR, the vertical synchronization signal of the reproduced video signal and the rotation of the motor of the rotary head drum are controlled by a drum motor servo circuit (not shown) so that they are synchronized and have a constant relationship. Therefore, the vertical blanking signal (V-BIJ) generated from the rotational phase detection pulse of the rotating head drum is stable, and the vertical synchronization signal in the reproduced video signal is disturbed due to changes in tape running speed during variable speed playback. Even if the rotary head drum is rotated stably, the V-BLK becomes a stable reference signal even if it is lost or lost.Furthermore, when switching between normal playback and variable speed playback, the reproduced video signal , phase fluctuation occurs, but the above V
By using -BL as a reference, the reference signal can be obtained steadily, and the phase fluctuation can be ignored.

Next, the operation for stabilizing the horizontal synchronization signal in the reproduced video signal that is reproduced in a predetermined relationship with the V-BLK will be described. First, as in the conventional example, after obtaining the output signal e of the %H killer circuit 4, in this embodiment, the signal e is supplied to a phase-locked loop (PLL) 9 to obtain a pulse signal g whose phase is lengthened. , thereby supplying the horizontal synchronization signal i stabilized at a constant period to H-IN of the character display controller 5. As a result, even if there is a drop or the like in the horizontal synchronization signal in the reproduced video signal, the horizontal synchronization signal i with a stable period is supplied to H-IN.

Therefore, the character display controller 5 can be configured to use not only the vertical synchronization signal but also the horizontal synchronization signal as a reference signal for providing addresses and the like for character display.

As a result of the above, the synchronization signal serving as the vertical and horizontal reference can be stably obtained even during variable speed reproduction, so that the character signal output from the character display controller 5 can be obtained without fluctuation in display position.

Next, details of the PLL 9 of this embodiment will be illustrated. The signal e is converted into a slope signal f by a slope (SLOPE) circuit 91. Then, a sampling hold (S/H) circuit 92
At this point, a sampling pulse h generated by a sampling pulse generator 95 is used to sample and hold the output g of the voltage controlled oscillator (VCO). slope signal f
Or assuming that the period of the output g of ■co changes, the sampling point of the slope signal f changes, so S/
The output voltage of the H circuit 92 is a signal according to the period error between the signal e and the signal g, and the slope circuit 91 and
The sampling and holding circuit 92 has the function of a PLL phase comparator. Then, the VCO 94 is controlled by the error signal that has passed through the low-pass filter 93, and is forced into a phase-locked state, and free-running oscillates at a frequency equal to the frequency of the signal e. Therefore, even if there is a drop in the signal e, the signal g remains stable. Become something.

[Effects of the Invention] By implementing the present invention, it is possible to obtain a character signal generation circuit in which vertical and horizontal reference signals supplied to a character display controller are stably supplied without dropouts or fluctuations even during variable speed reproduction. As a result, when superimposing characters such as text by inserting them into the playback video signal of a video tape recorder, the characters can be displayed without changing the display position or disappearing even during variable speed playback. A character signal generation circuit is obtained. Furthermore, characters can be displayed stably even when switching playback modes or displaying in EE mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
It is a timing chart corresponding to an answer part. FIG. 3 is a block diagram of a conventional character signal generation circuit, and FIG. 4 is a timing chart corresponding to the third response section. 1・−・−・−・−・・−Composite synchronization signal input terminal (SY
NCIN) 5----------Character display controller 6-------- Vertical blanking signal input terminal (V-BLK7-------------
- Monostable multivibrator (?IMV) 8...--
----OR circuit knee --- Phase locked loop (PLL) IN) Monostable multi-by-break (MM-FF) Block diagram of an embodiment of the present invention Fig. 1 Fig. 1-8 -Timing chart for fighting evil No. 20

Claims (1)

[Claims] In a character signal generation circuit that generates a character signal in response to an address signal formed based on a vertical synchronization signal and a horizontal synchronization signal, the vertical synchronization signal is generated from a rotational phase detection pulse of a rotating head drum. 1. A character signal generating circuit characterized in that the vertical blanking signal generated by the above-mentioned video signal is used, and a signal generated by a phase-locked loop using a horizontal synchronizing signal of a reproduced video signal as a phase reference is used as the horizontal synchronizing signal.